US3584241A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Schmitt trigger with controlled hysteresis
Assignee: Individual
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Filing: 1969-06-25
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Granted: 1971-06-08
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Expires: 1989-06-25
Abstract
Abstract An improved Schmitt trigger circuit in which hysteresis, the difference in input voltage level at which triggering on occurs as compared with the input level at which triggering off occurs, may be made zero or varied negatively or positively.
Inventors
- 👤 Michiyuki Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:43
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/2893
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
153 words
An emitter coupled binary circuit providing controlled hysteresis comprising two transistors each having an emitter, base and collector, means operably, connecting said collector of both said transistors to a supply voltage, means operably connecting said collector of a first of said transistors to said base of the second of said transistors, means interconnecting said emitters of said transistors, means operably connecting said emitters of both said transistors to ground, means for controlling hysteresis operably connecting said base of said second transistor to said collector of the same transistor, said last mentioned means including means operably connecting said collector of said second transistor to ground, said means for controlling hysteresis also including means operably connecting said base of said second transistor to ground, and means for applying a control pulse to said base of said first transistor thereby to bias said first transistor in accordance with the magnitude and polarity of said control pulse.
Claim 2
Dependent Claim
153 words
An emitter coupled binary circuit providing controlled hysteresis comprising two transistors each having an emitter, base and collector, means operably, connecting said collector of both said transistors to a supply voltage, means operably connecting said collector of a first of said transistors to said base of the second of said transistors, means interconnecting said emitters of said transistors, means operably connecting said emitters of both said transistors to ground, means for controlling hysteresis operably connecting said base of said second transistor to said collector of the same transistor, said last mentioned means including means operably connecting said collector of said second transistor to ground, said means for controlling hysteresis also including means operably connecting said base of said second transistor to ground, and means for applying a control pulse to said base of said first transistor thereby to bias said first transistor in accordance with the magnitude and polarity of said control pulse.
Claim 3
Dependent Claim
45 words
An emitter coupled binary circuit defined in claim 1 wherein said hysteresis controlling means comprises a plurality of resistor means and capacitor means positioned intermediate certain of said resistor means, and wherein said ground connecting means of said hysteresis controlling means including said capacitor means.
Claim 4
Dependent Claim
47 words
An emitter coupled binary circuit defined in claim 2 wherein said plurality of resistor means includes at least one variable resistor means operably connected between said second transistor collector and base and at least one variable resistor means operably connected between said second transistor base and ground.
Claim 5
Dependent Claim
49 words
An emitter coupled binary circuit defined in claim 2 wherein said plurality of resistor means includes fixed resistor means and variable resistor means in series relation connection between said collector and base, and fixed resistor means and variable resistor means in series relation connection between said base and ground.
Claim 6
Dependent Claim
64 words
An emitter coupled binary circuit defined in claim 1 wherein said hysteresis controlling means includes a first resistor means operably connected to said collector, a second resistor means operably connected to said first resistor means and to said base, and said ground connecting means for said collector operably connected intermediate said first and second resistor means, saId collector ground connecting means including capacitor means.
Claim 7
Dependent Claim
52 words
An emitter coupled binary circuit defined in claim 1 wherein said hysteresis controlling means include a first resistor and a second resistor connected in series operably connected between said collector and base, and said collector to ground connection means comprising a capacitor connected at the juncture of said first and second resistors.
Claim 8
Dependent Claim
51 words
An emitter coupled binary circuit defined in claim 1 wherein said transistors are of the NPN type, the supply voltage is positive, the first of said transistors is in a normally nonconducting state, the second of said transistors is in a normally conducting state, and the control pulse is positive going.
Claim 9
Dependent Claim
46 words
The emitter coupled binary circuit of claim 1 further defined wherein said transistors are of the PNP type, the supply voltage is negative, the first of said transistors is normally nonconducting, the second of said transistors is normally conducting, and the control pulse is negative going.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-07 | 1974-12-07 | 1975-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-07 | 1978-12-07 | 1979-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-07 | 1982-12-07 | 1983-06-08 | $7700.00 | Window Closed / Lapsed |