US3582943A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed digital-to-analog converter
Assignee: AT&T Inc
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Filing: 1968-12-09
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Granted: 1971-06-01
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Expires: 1988-12-09
Abstract
Abstract A high-speed digital-to-analog converter of the current-summing type is disclosed wherein a digital control register drives a plurality of current sources, all of the current sources being simultaneously switched on or off when digital inputs are applied. The time at which the simultaneous switching occurs is determined by the bias level of the current switches which is, in turn, determined by the characteristics of the digital control register.
Inventors
- 👤 David R Weller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:00
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
90 words
A digital-to-analog converter comprising: means for current summing including a plurality of parallelconnected current switches each having an ON state and an OFF state; means for receiving the simultaneous application of individual switching signals at each of said plurality of current switches whereby particular ones of said current switches are caused to change state; and means dependent upon the waveform characteristics of said individual switching signals for controlling said current switches, whereby said state changes are caused to begin simultaneously at a predetermined time after said switching signals are applied.
Claim 2
Dependent Claim
90 words
A digital-to-analog converter comprising: means for current summing including a plurality of parallelconnected current switches each having an ON state and an OFF state; means for receiving the simultaneous application of individual switching signals at each of said plurality of current switches whereby particular ones of said current switches are caused to change state; and means dependent upon the waveform characteristics of said individual switching signals for controlling said current switches, whereby said state changes are caused to begin simultaneously at a predetermined time after said switching signals are applied.
Claim 3
Dependent Claim
104 words
A digital-to-analog converter comprising means for current summing including a plurality of parallel-connected current switches; means for simultaneously applying either a first input voltage level or a second input voltage level to each of said plurality of current switches; and means for selectively controlling said current switches whereby all switching occurs at a predetermined time t after said simultaneous input voltages are applied where and where TR is the time required for said first input voltage level to change to said second input voltage level, and TF is the time required for said second input voltage to change to said first input voltage level.
Claim 4
Dependent Claim
104 words
A digital-to-analog converter comprising means for current summing including a plurality of parallel-connected current switches; means for simultaneously applying either a first input voltage level or a second input voltage level to each of said plurality of current switches; and means for selectively controlling said current switches whereby all switching occurs at a predetermined time t after said simultaneous input voltages are applied where and where TR is the time required for said first input voltage level to change to said second input voltage level, and TF is the time required for said second input voltage to change to said first input voltage level.
Claim 5
Dependent Claim
43 words
A digital-to-analog converter according to claim 2 wherein said means for selectively controlling said current switches comprises a threshold voltage v where and where H is the value of the difference between said second input voltage level and said first input voltage level.
Claim 6
Dependent Claim
89 words
A digital-to-analog converter comprising: means for current summing including a plurality of parallel-connected current switches each having an ON state and an OFF state; meanS for the simultaneous application of individual switching signals to each of said plurality of current switches whereby particular ones of said current switches are caused to change state; and means dependent upon the waveform characteristics of said individual switching signals for controlling said current switches, whereby said state changes are caused to begin simultaneously at a predetermined time after said switching signals are applied.
Claim 7
Dependent Claim
89 words
A digital-to-analog converter comprising: means for current summing including a plurality of parallel-connected current switches each having an ON state and an OFF state; meanS for the simultaneous application of individual switching signals to each of said plurality of current switches whereby particular ones of said current switches are caused to change state; and means dependent upon the waveform characteristics of said individual switching signals for controlling said current switches, whereby said state changes are caused to begin simultaneously at a predetermined time after said switching signals are applied.
Claim 8
Dependent Claim
119 words
A digital-to-analog converter comprising: means for current summing including a plurality of parallel-connected current switches; means for receiving the simultaneous application of either a first input voltage level or a second input voltage level at each of said plurality of current switches whereby particular ones of said current switches are caused to change state; and means for causing all of said state changes to occur at a predetermined time t after said simultaneous application of said switching signals where and where TR is the time required for said first input voltage level to change to said second input voltage level, and TF is the time required for said second input voltage to change to said first input voltage level.
Claim 9
Dependent Claim
119 words
A digital-to-analog converter comprising: means for current summing including a plurality of parallel-connected current switches; means for receiving the simultaneous application of either a first input voltage level or a second input voltage level at each of said plurality of current switches whereby particular ones of said current switches are caused to change state; and means for causing all of said state changes to occur at a predetermined time t after said simultaneous application of said switching signals where and where TR is the time required for said first input voltage level to change to said second input voltage level, and TF is the time required for said second input voltage to change to said first input voltage level.
Claim 10
Dependent Claim
51 words
A digital-to-analog converter according to claim 5 wherein said means for causing all of said state changes to occur at a predetermined time t comprises a threshold voltage v where and where H is the value of the difference between said second input voltage level and said first input voltage level.
Claim 11
Dependent Claim
92 words
A digital-to-analog converter including at least one stage comprising: a transistor; a resistor connected to the emitter of said transistor; a diode connected to the emitter of said transistor whereby a switching signal to be converted may be applied; means for biasing the base of said transistor to a voltage v, where the value of v is dependent upon the waveform characteristics of said switching signal; and a resistive network connected to the collector of said transistor, whereby the output signal appearing on the collector of said transistor can be appropriately weighted.
Claim 12
Dependent Claim
92 words
A digital-to-analog converter including at least one stage comprising: a transistor; a resistor connected to the emitter of said transistor; a diode connected to the emitter of said transistor whereby a switching signal to be converted may be applied; means for biasing the base of said transistor to a voltage v, where the value of v is dependent upon the waveform characteristics of said switching signal; and a resistive network connected to the collector of said transistor, whereby the output signal appearing on the collector of said transistor can be appropriately weighted.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |