Core memory selection matrix

Claim 2

A magnetic memory matrix comprising a plurality of magnetic bistable storage elements, a driving circuit including a current pulse carrying drive line magnetically coupled to each of said elements said current pulse energizing said storage elements by means of a switching magnetic field of sufficient magnitude provided by said current pulse, said driving circuit providing that magnitude of current necessary to result in said switching, said driving circuit including a read current source connected to a first end of said drive line, a write current source connected to the other end of said drive line, a first set of two transistors having their emitter-collector paths serially connected between a potential source and one end of said drive line, a second set of two transistors having their emitter collector paths serially connected between said source of potential and the other end of said drive line, means for simultaneously selecting one of said transistors in each of said first and second sets of said transistors, and means for selectively addressing either one or the other of the remaining transistors in said first or said second set of transistors for completing a current path of either a first or a second direction through said drive line.

Claim 3

A magnetic memory comprising an array of magnetic elements each arranged in rows and columns, drive lines coupling each of said elements along the respective rows and columns, a selectively operable source of read current coupled to one end of each drive line, a selectively operable source of write current coupled to the other end of each drive line, a first selectively operable switch connecting one end of a drive line to a reference point and comprising first and second normally nonconductive transistors having their collector emitter paths serially coupled between the associated drive line and said reference point, a second selectively operable switch connecting the other end of a drive line to said reference point and comprising third and fourth normally nonconductive transistors having their collector emitter path serially connected between the associated drive line and said reference point, addressing means for selecting one of said current sources and the appropriate one of said switches so as to provide current from the selected current source to flow along said drive line, means for sending said first or said third transistor conductive for determining the source current direction through said associated drive line, and addressing means for selecting said second and fourth transistor for selecting said associated drive Line.

Claim 4

A magnetic memory comprising an array of magnetic elements each arranged in rows and columns, drive lines coupling each of said elements along the respective rows and columns, a selectively operable source of read current coupled to one end of each drive line, a selectively operable source of write current coupled to the other end of each drive line, a first selectively operable switch connecting one end of a drive line to a reference point and comprising first and second normally nonconductive transistors having their collector emitter paths serially coupled between the associated drive line and said reference point, a second selectively operable switch connecting the other end of a drive line to said reference point and comprising third and fourth normally nonconductive transistors having their collector emitter path serially connected between the associated drive line and said reference point, addressing means for selecting one of said current sources and the appropriate one of said switches so as to provide current from the selected current source to flow along said drive line, means for sending said first or said third transistor conductive for determining the source current direction through said associated drive line, and addressing means for selecting said second and fourth transistor for selecting said associated drive Line.

Claim 5

A magnetic memory comprising an array of magnetic elements arranged in rows and columns, drive lines coupling each of said elements along the respective rows and columns, each pair of drive lines in said array being terminated at their first and second set of ends by first and second pairs of diodes oppositely poled with respect to the other and having the electrodes thereof remote from the drive line commonly terminated, a first plurality of transistors, the collector emitter path of each transistor of said first plurality respectively connected between each common diode termination of the first set of drive line ends and a first point, a second plurality of transistors, the collector emitter path of each transistor of said second plurality respectively connected between each common diode termination of the second set of drive line ends and a second point, a read transistor having its emitter-collector path connected between said first point and a point of operating potential, a write transistor having its emitter collector path connected between said second point and a point of operating potential, a write current source point provided at one end of each of the first lines of said set of drive line end with a first polarity and at one end of each the second lines of said first set of drive line end pairs with a second polarity, a read current source point provided at one end of each of the first lines of said second set of drive line end pairs with a first polarity and at one end of each of the second lines of said second set of drive line end pairs with a second polarity, first selection means selectively connected to said current source points and selecting one of a group of first ones of said sets or a group of second ones of said sets of drive lines, and second selection means selectively energizing a transistor of each of said first and second plurality of transistors for selecting a pair of said drive lines within said group, said first and said second selection means thereby energizing a single one of said drive lines.

Claim 6

A magnetic memory comprising an array of magnetic elements arranged in rows and columns, drive lines coupling each of said elements along the respective rows and columns, each pair of drive lines in said array being terminated at their first and second set of ends by first and second pairs of diodes oppositely poled with respect to the other and having the electrodes thereof remote from the drive line commonly terminated, a first plurality of transistors, the collector emitter path of each transistor of said first plurality respectively connected between each common diode termination of the first set of drive line ends and a first point, a second plurality of transistors, the collector emitter path of each transistor of said second plurality respectively connected between each common diode termination of the second set of drive line ends and a second point, a read transistor having its emitter-collector path connected between said first point and a point of operating potential, a write transistor having its emitter collector path connected between said second point and a point of operating potential, a write current source point provided at one end of each of the first lines of said set of drive line end with a first polarity and at one end of each the second lines of said first set of drive line end pairs with a second polarity, a read current source point provided at one end of each of the first lines of said second set of drive line end pairs with a first polarity and at one end of each of the second lines of said second set of drive line end pairs with a second polarity, first selection means selectively connected to said current source points and selecting one of a group of first ones of said sets or a group of second ones of said sets of drive lines, and second selection means selectively energizing a transistor of each of said first and second plurality of transistors for selecting a pair of said drive lines within said group, said first and said second selection means thereby energizing a single one of said drive lines.

Claim 7

The combination of claim 3 wherein said first selection means comprises a plurality of AND gates, a plurality of transistors, each transistor responsive to the output of a respective AND gate, each transistor having a diode interconnecting the base and emitter electrode thereof, and a first resistor common to all emitter electrodes for applying a first potential to each transistor, and a plurality of a second resistors, each applying a second source of potential to the base electrode of each transistor, each collector electrode of each said transistor uniquely energizable to provide the desired current flow upon a corresponding energization of said AND gates.

Claim 8

In a magnetic memory matrix, the combination comprising a plurality of magnetic storage elements, a plurality of drive lines coupled to the respective storage elements, a plurality of current sources for generating a current flow of fixed amplitudes, each source having an output respectively coupled to and in series current relationship with one end of a respective drive line, each current source having associated therewith a unidirectional current switch, a first plurality of selection switches coupled to the other end of said drive lines, a second plurality of selection switches coupled to said plurality of current sources, means coupled to said second plurality of selection switches for selecting one of said current sources and establishing a flow of said fixed amplitude current through the unidirectional current switch associated therewith, means coupled to said first plurality of selection switches for selecting one of said drive lines and reverse biasing said unidirectional current switch, thereby diverting said fixed amplitude current along said drive line, said current having a pulse form with a magnitude in said drive line which equals the magnitude of the current provided by said selected current source.

Claim 9

In a magnetic memory matrix, the combination comprising a plurality of magnetic storage elements, a plurality of drive lines coupled to the respective storage elements, a plurality of current sources for generating a current flow of fixed amplitudes, each source having an output respectively coupled to and in series current relationship with one end of a respective drive line, each current source having associated therewith a unidirectional current switch, a first plurality of selection switches coupled to the other end of said drive lines, a second plurality of selection switches coupled to said plurality of current sources, means coupled to said second plurality of selection switches for selecting one of said current sources and establishing a flow of said fixed amplitude current through the unidirectional current switch associated therewith, means coupled to said first plurality of selection switches for selecting one of said drive lines and reverse biasing said unidirectional current switch, thereby diverting said fixed amplitude current along said drive line, said current having a pulse form with a magnitude in said drive line which equals the magnitude of the current provided by said selected current source.