Device for identifying a fingerprint pattern

Claim 3

A device as claimed in claim 1, wherein said pattern from which said coder means produces electrical signals is a fingerprint pattern.

Claim 4

A device as claimed in claim 1, in which said first circuit means is connected to receive the coder output signals via a processing memory for temporarily retaining a prescribed number of said signals in a matrix array; said first circuit means being provided in the form of a singular point detector for examining in turn each of the signals in the matrix array together with a prescribed number of neighboring signals and for identifying from such examination any signals significant of singular points; said first and second circuit means being connected via a singular point memory for temporarily holding signals significant of any singular points identified by the singular point detector; in which a monitor is provided for controlling operation of the singular point memory and singular point detector; in which said second circuit means and third circuit means are combined in a characteristic point detector for determining, from the signal significant of a singular point stored in the singular point memory, and from the signals significant of points surrounding said singular point, the slope of the tangent to the pattern line at said point; said fourth circuit means being provided in the form of a leading point detector for examining a relatively large area around each point to determine if it is a leading point and for canceling any leading points appearing at the output of the characteristic point detector, thereby allowing only characteristic points to take part in the identification process; and further including a recorder for making a record of the coordinates and tangent slopes of any characteristic points, a library for storing data, transferring means for transferring such details of the characteristic points into said library for permanent storage, and a timer providing signals for synchronizing operation of the elements of the device.

Claim 5

A device as claimed in claim 3, in which said coder comprises a conventional television camera, a threshold circuit, And first and second majority decision circuits.

Claim 6

A device as claimed in claim 4, in which said television camera is arranged to view, in successive, vertically spaced, horizontal scans controlled by time base signals from the timer, the image of the pattern and to produce video signals significant of the pattern image.

Claim 7

A device as claimed in claim 5, in which the threshold circuit is arranged to receive video signals from the television camera and transmit only those of magnitudes greater than a predetermined threshold value, to provide binary coded first video-logical signals.

Claim 8

A device as claimed in claim 6, in which the first majority decision circuit is connected to receive at its input an uneven number of successive first video-logical signals from one horizontal scan of the television camera and to provide a second video-logical signal of the same logical value as the first video-logical signal value of which there is a greater number.

Claim 9

A device as claimed in claim 7, in which the second majority decision circuit is connected to receive at its input an uneven number of second video-logical signals, one from each of the same number of successive horizontal scans, which represent a vertical line on the pattern image, and to provide an output signal of the same logical value as the second video-logical signal value of which there is a greater number.

Claim 10

A device as claimed in claim 8, in which the processing memory comprises a number of shift registers which may be connected in series to form a single composite shift register, and at least one of which may have its output division connected to its input division so as to form a ring register.

Claim 11

A device as claimed in claim 9, in which the singular point detector comprises a transfer circuit, a search computer, and an analogue decision element.

Claim 12

A device as claimed in claim 10, in which the transfer circuit is connected to the processing memory to reproduce preselected signals held in the processing memory, and in which the search computer is connected to receive the reproduced signals from the transfer circuit and arranged to store the reproduced signals in a prescribed way for a prescribed time.

Claim 13

A device as claimed in claim 11, in which the preselected signals to be reproduced are signals corresponding to a number of points immediately surrounding the point being examined.

Claim 14

A device as claimed in claim 10, in which the search computer is a ring register which holds the reproduced signals for a prescribed time by cycling them around its divisions.

Claim 15

A device as claimed in claim 10, in which the analogue decision element is connected to receive signals from the search computer and adapted to provide a given output if the input signals fulfill a prescribed condition indicating that the point being examined is a singular point.

Claim 16

A device as claimed in claim 9, in which the monitor comprises a number of counters connected to receive signals from the timer and arranged to operate to control the singular point detector and the singular point memory and to provide signals identifying the point being examined.

Claim 17

A device as claimed in claim 15, in which the singular point memory comprises a second transfer circuit and a memory circuit, and in which the second transfer circuit is connected to receive instructions from the decision element of the singular point detector and signals from the monitor, and which operates to transmit to the memory circuit identifying signals from the monitor under the control of the decision element.

Claim 18

A device as claimed in claim 16, in which the identifying signals transmitted by the second transfer circuit identify a point classified as a singular point, and in which the second transfer circuit also transmits to the memory circuit clearing signals generated by the monitor and arranged to clear the singular point memory when all singular points in each group of signals corresponding to one scan line on the pattern image have been identifiEd.

Claim 19

A device as claimed in claim 16, in which the memory circuit is arranged to store the identifying signals for a prescribed time limited by the clearing pulses from the monitor.

Claim 20

A device as claimed in claim 3, in which the characteristic point detector comprises a condition monitor, a sequence detector, and a second analogue decision element.

Claim 21

A device as claimed in claim 19, in which the condition monitor comprises first circuitry connected to the processing memory and operating to control the cycling of signals therein when at least one register of the processing memory is connected as a ring register, and operating to provide instructions to reconnect the register as a composite shift register and to advance the signals held in the register by one division to proceed to the processing of the next point; second circuitry connected to the output division of each register of the processing memory and operating to select any one of the said output divisions and to reproduce the signal occupying said division; and third circuitry operating to identify and record details of the register of which said output division is a part.

Claim 22

A device as claimed in claim 19, in which the sequence detector comprises first circuits connected to receive via the condition monitor successive signals from a given register of the processing memory, of which signals the first represents a singular point, and to detect and record details of the point at the remote end of a sequence of signals of the same logical value as the first signal and in the same register; second circuits connected to receive from the processing memory successive signals from registers on either side of the given register and to detect similar sequences of signals; memory circuits connected to record details of the points at the ends of each sequence; and third circuits connected to the condition monitor to provide a signal for controlling the selection of registers to follow said given register.

Claim 23

A device as claimed in claim 21, in which the second analogue decision element is connected to receive information stored in the memory circuits of the sequence detector and arranged to perform logical operations on this information to decide if a given singular point is a characteristic point and, if so, to calculate a unique property of a pattern line ending at said point.

Claim 24

A device as claimed in claim 22, in which the property calculated by the second analogue decision element is the slope of the tangent to the pattern line at said point.

Claim 25

A device as claimed in claim 3, in which the leading point detector comprises two counters and a suppressor circuit, and in which each of the counters is connected to receive signals from divisions of registers on a respective side of the central register of the processing memory and to advance by one step each time every such signal is of the same type, and to provide an output every time a prescribed number of such advances of one step have been made in succession, as indicated by the counter reaching a prescribed value.

Claim 26

A device as claimed in claim 24, in which the suppressor circuit is connected to receive the outputs from the counters and to provide a suppressor output signal whenever either counter indicates the presence of a leading point.

Claim 27

A device as claimed in claim 3, in which the recorder comprises an instruction element, a transfer circuit, a buffer memory and a recording device.

Claim 28

A device as claimed in claim 26, in which the instruction element is connected to receive instructions from the condition monitor and also data representative of successive characteristic points, in which the transfer circuit is connected to receive instructions and data from the instruction element and suppressor signals from the linear point detector, and arranged to transmit said data and instructions in the absence of a suppressor signal and in which the buffer memory is connected to receive said data and instructions and to store them teMporarily.

Claim 29

A device as claimed in claim 26, in which the recording device is connected to receive the data from the buffer memory and is provided with means for making a permanent record of the data and for passing the data into a library.

Claim 30

A device as claimed in claim 18, in which the characteristic point detector comprises a condition monitor, a sequence detector, and a second analogue decision element.

Claim 31

A device as claimed in claim 29, in which the condition monitor comprises first circuitry connected to the processing memory and operating to control the cycling of signals therein when at least one register of the processing memory is connected as a ring register, and operating to provide instructions to reconnect the register as a composite shift register and to advance the signals held in the register by one division to proceed to the processing of the next point; second circuitry connected to the output division of each register of the processing memory and operating to select any one of the said output divisions and to reproduce the signal occupying said division; and third circuitry operating to identify and record details of the register of which said output division is a part.

Claim 32

A device as claimed in claim 30, in which the sequence detector comprises first circuits connected to receive via the condition monitor successive signals from a given register of the processing memory, of which signals the first represents a singular point, and to detect and record details of the point at the remote end of a sequence of signals of the same logical value as the first signal and in the same register; second circuits connected to receive from the processing memory successive signals from registers on either side of the given register and to detect similar sequences of signals; memory circuits connected to record details of the points at the ends of each sequence; and third circuits connected to the condition monitor to provide a signal for controlling the selection of registers to follow said given register.

Claim 33

A device as claimed in claim 31, in which the second analogue decision element is connected to receive information stored in the memory circuits of the sequence detector and arranged to perform logical operations on this information to decide if a given singular point is a characteristic point and, if so, to calculate a unique property of a pattern line ending at said point.

Claim 34

A device as claimed in claim 32, in which the property calculated by the second analogue decision element is the slope of the tangent to the pattern line at said point.

Claim 35

A device as claimed in claim 33, in which the leading point detector comprises two counters and a suppressor circuit, and in which each of the counters is connected to receive signals from divisions of registers on a respective side of the central register of the processing memory and to advance by one step each time every such signal is of the same type, and to provide an output every time a prescribed number of such advances of one step have been made in succession, as indicated by the counter reaching a prescribed value.

Claim 36

A device as claimed in claim 34, in which the suppressor circuit is connected to receive the outputs from the counters and to provide a suppressor output signal whenever either counter indicates the presence of a loading point.

Claim 37

A device as claimed in claim 35, in which the recorder comprises an instruction element, a transfer circuit, a buffer memory and a recording device.