US3582797A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase comparison control system
Assignee: Xerox Corp
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Filing: 1968-05-08
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Granted: 1971-06-01
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Expires: 1988-05-08
Abstract
Abstract A phase comparison control system wherein the element to be controlled is a voltage controlled frequency source. A three stage counter is disclosed which is upcounted by a reference pulse train and downcounted by a feedback pulse train. When both frequencies are equal, the output is a square wave wherein the average value thereof is proportional to the phase difference of the two input frequencies. A digitally operated filter is used to generate the analog voltage for control of the frequency source.
Inventors
- 👤 Alton F Riethmeier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:55
CPC Classifications
H; H03; H03L; H03L7/00; H02; H02P; H02P23/00; H02P23/18; H02P23/186; H02P25/00; H02P25/02; H02P25/022; H02P25/024; H02P5/00; H02P5/46; H02P5/52; H02P5/56; Y; Y10; Y10S; Y10S388/00; Y10S388/90; Y10S388/906; Y10S388/907; Y10S388/908
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
338 words
A phase comparison control system for maintaining an operating frequency signal in synchronization with a reference frequency signal comprising: means for comparing said operating frequency signal and said reference frequency signal and generating rectangular shaped pulses the time duration thereof being directly proportional to the phase difference between said signals, said comparing means comprising: flip-flop circuit means for generating said rectangular shaped pulses, said flip-flop circuit means comprising first, second, and third flip-flop circuits being set in the order of the first, second, and third flip-flop circuits by the reference frequency signal, and said flip-flop circuits being reset in the order of the third, second, and first flip-flop circuits by the operating frequency signal, said second flip-flop circuit remaining in a set condition when said reference signal frequency is greater than said operating signal frequency and remaining in a reset condition when said operating signal frequency is greater than said reference signal frequency, mean for integrating said rectangular-shaped pulses for generating an output voltage about a median voltage, wherein said median voltage is the value indicative of said operating signal frequency being equal to said reference signal frequency, said integrating means comprising: first means for generating a first current of one polarity when said operating signal frequency is greater than said reference signal frequency, second means for generating a second current of the other polarity when said reference signal frequency is greater than said operating signal frequency, and impedance means coupled to said first and second means for generating said output voltage in response to said first and second currents, voltage controlled oscillator means for generating said operating frequency signal in response to said output voltage, said output voltage being higher in value than said voltage when said operating signal frequency is less than said reference signal frequency thereby tending to increase said operating signal frequency, and said output voltage being lower in value than said median voltage when said operating signal frequency is greater than said reference signal frequency thereby tending to decrease said operating signal frequency.
Claim 2
Dependent Claim
338 words
A phase comparison control system for maintaining an operating frequency signal in synchronization with a reference frequency signal comprising: means for comparing said operating frequency signal and said reference frequency signal and generating rectangular shaped pulses the time duration thereof being directly proportional to the phase difference between said signals, said comparing means comprising: flip-flop circuit means for generating said rectangular shaped pulses, said flip-flop circuit means comprising first, second, and third flip-flop circuits being set in the order of the first, second, and third flip-flop circuits by the reference frequency signal, and said flip-flop circuits being reset in the order of the third, second, and first flip-flop circuits by the operating frequency signal, said second flip-flop circuit remaining in a set condition when said reference signal frequency is greater than said operating signal frequency and remaining in a reset condition when said operating signal frequency is greater than said reference signal frequency, mean for integrating said rectangular-shaped pulses for generating an output voltage about a median voltage, wherein said median voltage is the value indicative of said operating signal frequency being equal to said reference signal frequency, said integrating means comprising: first means for generating a first current of one polarity when said operating signal frequency is greater than said reference signal frequency, second means for generating a second current of the other polarity when said reference signal frequency is greater than said operating signal frequency, and impedance means coupled to said first and second means for generating said output voltage in response to said first and second currents, voltage controlled oscillator means for generating said operating frequency signal in response to said output voltage, said output voltage being higher in value than said voltage when said operating signal frequency is less than said reference signal frequency thereby tending to increase said operating signal frequency, and said output voltage being lower in value than said median voltage when said operating signal frequency is greater than said reference signal frequency thereby tending to decrease said operating signal frequency.
Claim 3
Dependent Claim
39 words
The system as set forth in claim 1 further including alternating current motor means coupled to said voltage controlled oscillator means for increasing and decreasing the rotational speed thereof in response to the increasing and decreasing operating signal frequencies.
Claim 4
Dependent Claim
38 words
The system as set forth in claim 1 fUrther including direct current motor means coupled directly to said integrating means for increasing and decreasing the rotational speed thereof in response to the increasing and decreasing operating signal frequencies.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |