US3582677A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse spacing discriminator circuit
Assignee: Raytheon Co
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Filing: 1969-12-16
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Granted: 1971-06-01
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Expires: 1989-12-16
Abstract
Abstract A pulse spacing discriminator circuit may be formed on a single semiconductor substrate utilizing five MOS field effect transistors and a maximum of four field effect transistor switch resistors. The circuit provides an output pulse if the spacing between successive input pulses is greater than a predetermined time interval. The output pulse terminates upon receipt of the next input pulse.
Inventors
- 👤 Carroll R Perkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:25
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
187 words
A pulse spacing discriminator circuit comprising: first, second, third, fourth and fifth field effect transistors each having a first electrode, a second electrode and a control electrode; the respective first electrodes of each of said transistors being connected together; the respective second electrodes of said second and third transistors being connected together; the respective second electrodes of said fourth and fifth transistors being connected together; the second electrode of said first transistor being coupled to the control electrode of said second transistor; the interconnected second electrodes of said second and third transistors being coupled to the control electrode of said fourth transistor; means for applying input pulses to the control electrode of said first transistor and to the control electrode of said fifth transistor; means coupled between the first and second electrodes of each of said transistors for furnishing operating potentials for said transistors; means for obtaining an output signal at the interconnected second electrodes of said fourth and fifth transistors; and means for applying a feedback signal from said interconnected second electrodes of said fourth and fifth transistors to the control electrode of said third transistor.
Claim 2
Dependent Claim
187 words
A pulse spacing discriminator circuit comprising: first, second, third, fourth and fifth field effect transistors each having a first electrode, a second electrode and a control electrode; the respective first electrodes of each of said transistors being connected together; the respective second electrodes of said second and third transistors being connected together; the respective second electrodes of said fourth and fifth transistors being connected together; the second electrode of said first transistor being coupled to the control electrode of said second transistor; the interconnected second electrodes of said second and third transistors being coupled to the control electrode of said fourth transistor; means for applying input pulses to the control electrode of said first transistor and to the control electrode of said fifth transistor; means coupled between the first and second electrodes of each of said transistors for furnishing operating potentials for said transistors; means for obtaining an output signal at the interconnected second electrodes of said fourth and fifth transistors; and means for applying a feedback signal from said interconnected second electrodes of said fourth and fifth transistors to the control electrode of said third transistor.
Claim 3
Dependent Claim
101 words
A pulse spacing discriminator circuit according to claim 1 wherein said means for furnishing operating potentials comprises: a source of potential having a first terminal and a second terminal, said first terminal being connected to the first electrodes of each of said transistors, a first resistive device coupled between said second terminal and the second electrode of said first transistor, a second resistive device coupled between said second terminal and the interconnected second electrodes of said second and third transistors, and a third resistive device coupled between said second terminal and the interconnected second electrodes of said fourth and fifth transistors.
Claim 4
Dependent Claim
21 words
A pulse spacing discriminator circuit according to claim 2 wherein each said resistive device is a field effect transistor switch resistor.
Claim 5
Dependent Claim
41 words
A pulse spacing discriminator circuit according to claim 3 wherein each said field effect transistor switch resistor has a channel width-to-length ratio approximately an order of magnitude less than that of said first, second, third, fourth and fifth field effect transistors.
Claim 6
Dependent Claim
25 words
A pulse spacing discriminator circuit according to claim 4 wherein each said field effect transistor switch resistor is biased to essentially a saturated conductive condition.
Claim 7
Dependent Claim
34 words
A pulse spacing discriminator circuit according to claim 1 wherein a field effect transistor switch resistor is coupled between the second electrode of said first transistor and the control electrode of said second transistor.
Claim 8
Dependent Claim
40 words
A pulse spacing discriminator circuit according to claim 6 wherein said field effect transistor switch resistor has a channel width-to-length ratio approximately an order of magnitude less than that of said first, second, third, fourth and fifth field effect transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |