Method and apparatus for making semiconductor devices
Abstract
Abstract MASKING APPARATUS AND TECHNIQUES ARE DISCLOSED FOR THE FABRICATION OF OBJECTS SUCH AS HIGH FREQUENCY SEMICONDUCTOR DEVICES THAT HAVE EXTREMELY CLOSELY SPACED ELEMENTS. FOR EXAMPLE, THE INVENTION CAN BE USED TO POSITION AN ELONGATED EMITTER ELECTRODE BETWEEN TWO ELONGATED BASE ELECTRODES. IN THE SPACE ON A WATER ORDINARILY OCCUPIED BY A SINGLE CONVENTIONAL TRANSISTOR, A NUMBER OF TRANSISTORS ARE FABRICATED WITH PHOT-RESIST AND MASKING. THE MASK USED TO DEFINE THE EMITTER ELECTRODES IN SUCH A CASE COMPRISES AN ARRAY OF STRIPES. HOWEVER, MOST OF THE STRIPES ARE SLIGHTLY MISALIGNED WITH RESPECT TO THE CORRESPONDING PAIR OF BASE ELECTRODES OR ARE SLIGHTLY TOO LARGE OR TOO SMALL. THUS, EVEN IF THE MASK IS SLIGHTLY MISALIGNED, AT LEAST ONE OF THE MISALIGNED STRIPES ON THE MASK IS FOUND TO BE CORRECTLY ALIGNED WITH THE PAIR OF BASE ELECTRODES. AND EVEN IF THE PHOTO-RESIST IS SLIGHTLY UNDER-EXPOSED OR OVER-EXPOSED, AT LEAST ONE OF THE DIFFERENT SIZED STRIPES COMPENSATES FOR IT. CONSEQUENTLY, PRODUCTION OF AT LEAST ONE GOOD TRANSISTOR IS ASSURED EVEN IF THE MASK IS MISALIGNED OR THE EXPOSURE TIME IS OTHER T HAN OPTIMUM. AND BECAUSE THE COMBINED AREA OF THE GOOD AND BAD TRANSISTORS ON THE WAFER IS THE SAME AS THE AREA OF A CONVENTIONAL TRANSISTOR, NO PART OF THE WAFER IS WASTED.
Inventors
- 👤 Joseph Kocsis
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |