US3581284A
Expired / Lapsed
US
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Randomly accessed noninterfering input-output data accumulator
Assignee: Northrop Grumman Space and Mission Systems Corp
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Filing: 1968-06-03
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Granted: 1971-05-25
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Expires: 1988-06-03
Abstract
Abstract There is disclosed a data accumulator suitable for use in oil field supervisory control systems or, more generally, in various process control or other data processing systems wherein it is desired to accumulate total at the remote location at any time without destroying or interfering with the accumulating total regardless of when the readout command is received. In order to accomplish this, there is provided a shift register adapted to contain the total count data in the form of a binary word having a predetermined number of bits. The shift register is connected in a feedback loop such that its contents may be serially read out and passed through a specialized adding circuit which either transmits the register content in unchanged form or adds one to the total content depending upon whether the adding circuit has been actuated by receipt of an add command from a bistable input buffer means which receives the input unit event counting pulse. The output of the adding circuit is applied as feedback to the input of the shift register in such a fashion that the register content is continuously circulating. The timing parameters of the circuit are chosen so that the total duration of the input unit event count pulse is greater than the total time duration of the complete work content of the shift register. On this basis, the adding circuit logic can be shown to produce a correct and unambiguous result regardless of when the input pulse arrives or when a readout is desired. The online readout is, of course, taken from the adding circuit.
Inventors
- 👤 Ronald B Selden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:20
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/504
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
149 words
Data processing circuitry for adding one to a digitally encoded binary number comprising: circuitry having a given word capacity; a. input means to present to said circuitry a binary coded number having a plurality of orders of significance each having a coefficient which is either zero or one, said coefficient being presented sequentially in ascending order of significance; said binary coded number having a duration greater than the total duration of said word content of said circuitry; b. circuit means to sequentially produce the one''s complement of said coefficient as they are presented, means responsive to the first zero coefficient of any order of said number for controlling said circuit means; and, c. circuit means responsive to the occurrence of said first zero coefficient to thereafter reproduce without change the remaining coefficients of said higher orders of said binary number whereby said complete binary number is increased by one.
Claim 2
Dependent Claim
149 words
Data processing circuitry for adding one to a digitally encoded binary number comprising: circuitry having a given word capacity; a. input means to present to said circuitry a binary coded number having a plurality of orders of significance each having a coefficient which is either zero or one, said coefficient being presented sequentially in ascending order of significance; said binary coded number having a duration greater than the total duration of said word content of said circuitry; b. circuit means to sequentially produce the one''s complement of said coefficient as they are presented, means responsive to the first zero coefficient of any order of said number for controlling said circuit means; and, c. circuit means responsive to the occurrence of said first zero coefficient to thereafter reproduce without change the remaining coefficients of said higher orders of said binary number whereby said complete binary number is increased by one.
Claim 3
Dependent Claim
142 words
A randomly accessed noninterfering input-output data accumulator comprising: a. a data shift register having an input and an output for handling a digitally encoded word; b. a feedback loop comprising an adding circuit and connected to serially read the content of said data shift register from its output through the adding circuit and back to the input of said register; c. bistable means responsive to receipt of a unit event count pulse input, said bistable means being connected to actuate said adding circuit upon receipt of said pulse to add one to the word content of said register as said word passes through said adding circuit, said unit event count pulse having a duration greater than the total duration of said word content of said register; and d. means to serially apply the output of said adding circuit to a utilization circuit.
Claim 4
Dependent Claim
142 words
A randomly accessed noninterfering input-output data accumulator comprising: a. a data shift register having an input and an output for handling a digitally encoded word; b. a feedback loop comprising an adding circuit and connected to serially read the content of said data shift register from its output through the adding circuit and back to the input of said register; c. bistable means responsive to receipt of a unit event count pulse input, said bistable means being connected to actuate said adding circuit upon receipt of said pulse to add one to the word content of said register as said word passes through said adding circuit, said unit event count pulse having a duration greater than the total duration of said word content of said register; and d. means to serially apply the output of said adding circuit to a utilization circuit.
Claim 5
Dependent Claim
28 words
Apparatus as in claim 2 and further including means connected to change the state of said bistable means responsive to completion of said addition by said adding circuit.
Claim 6
Dependent Claim
203 words
Data processing circuitry comprising: a. a shift register having an input and an output for handling a binary number; b. a feedback loop comprising an adding circuit connected to serially read the content of said shift register from its output through the adding circuit and back to the input of said shift register, said serial readout starting with the lowest order of said binary number and continuing sequentially to progressively higher orders; c. said adding circuit comprising command responsive means responsive to a unit event count pulse having a duration greater than the total duration of said word content of said register to produce the one''s complement of the coefficient of each order of said binary number, the first zero coefficient of any order of said number being transmitted through said adding circuit, and means responsive to transmission of said first zero coefficient to transmit the remaining coefficients of higher orders of said binary number through said adding circuit and said feedback loop without change whereby a complete circulation of the entire number in said shift register through said adding circuit increases the numerical magnitude of the binary number in said shift register by one when said command responsive means has been actuated.
Claim 7
Dependent Claim
203 words
Data processing circuitry comprising: a. a shift register having an input and an output for handling a binary number; b. a feedback loop comprising an adding circuit connected to serially read the content of said shift register from its output through the adding circuit and back to the input of said shift register, said serial readout starting with the lowest order of said binary number and continuing sequentially to progressively higher orders; c. said adding circuit comprising command responsive means responsive to a unit event count pulse having a duration greater than the total duration of said word content of said register to produce the one''s complement of the coefficient of each order of said binary number, the first zero coefficient of any order of said number being transmitted through said adding circuit, and means responsive to transmission of said first zero coefficient to transmit the remaining coefficients of higher orders of said binary number through said adding circuit and said feedback loop without change whereby a complete circulation of the entire number in said shift register through said adding circuit increases the numerical magnitude of the binary number in said shift register by one when said command responsive means has been actuated.
Claim 8
Dependent Claim
285 words
A randomly accessed noninterfering input-output data accumulator comprising: a. adding circuit means to add one to a digitally encoded plural bit binary number transmitted through said adding circuit; b. a shift register containing a representation of a digitally encoded binary number; c. means connecting the output of said shift register to the input of said adding circuit and further means connecting the output of said adding circuit to the input of saId shift register to form a closed feedback loop; d. means to supply a clock signal to said shift register to continuously serially move the content of said shift register through said adding circuit and back into said shift register; e. buffer circuit input means for receiving a unit event count pulse; f. an AND gate circuit connected to receive a signal output from said buffer circuit at one of its inputs and to receive a word frame pulse input signal at another of its inputs; g. said word frame pulse signal having a period equal to the sum of the total periods of the clock pulses in the total representation of all of the bits in said binary number in said shift register and said unit event input pulse having a period of duration greater than the period of said word frame pulse; h. means connecting the output of said AND gate circuit to enable said adding circuit to commence addition upon the coincident occurrence of a unit event count pulse and said word frame pulse; i. means to apply a signal from said adding circuit to said input buffer circuit indicating completion of said addition process; and, j. means to derive an online output reading from the output of said adding circuit.
Claim 9
Dependent Claim
285 words
A randomly accessed noninterfering input-output data accumulator comprising: a. adding circuit means to add one to a digitally encoded plural bit binary number transmitted through said adding circuit; b. a shift register containing a representation of a digitally encoded binary number; c. means connecting the output of said shift register to the input of said adding circuit and further means connecting the output of said adding circuit to the input of saId shift register to form a closed feedback loop; d. means to supply a clock signal to said shift register to continuously serially move the content of said shift register through said adding circuit and back into said shift register; e. buffer circuit input means for receiving a unit event count pulse; f. an AND gate circuit connected to receive a signal output from said buffer circuit at one of its inputs and to receive a word frame pulse input signal at another of its inputs; g. said word frame pulse signal having a period equal to the sum of the total periods of the clock pulses in the total representation of all of the bits in said binary number in said shift register and said unit event input pulse having a period of duration greater than the period of said word frame pulse; h. means connecting the output of said AND gate circuit to enable said adding circuit to commence addition upon the coincident occurrence of a unit event count pulse and said word frame pulse; i. means to apply a signal from said adding circuit to said input buffer circuit indicating completion of said addition process; and, j. means to derive an online output reading from the output of said adding circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-24 | 1974-11-23 | 1975-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-24 | 1978-11-23 | 1979-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-24 | 1982-11-23 | 1983-05-25 | $7700.00 | Window Closed / Lapsed |