US3581108A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single output selecting circuit employing a plurality of interlocked nor-gates
Assignee: AT&T Inc
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Filing: 1968-12-05
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Granted: 1971-05-25
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Expires: 1988-12-05
Abstract
Abstract A plurality of NOR gates are arranged with the output of each gate connected to an associated output terminal and to an input of every other gate. Energization of a selected output terminal, inhibits the operation of each gate other than the one associated with the selected output terminal thereby latching the one associated with the selected terminal in an energized condition and the nonselected terminals in a nonenergized condition.
Inventors
- 👤 Irving V Eisenmenger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:26
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/038; H03K17/00; H03K17/002; H03K17/007
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
152 words
A logic latching circuit, comprising: a plurality of three or more output terminals; a plurality of three or more input terminals, each of said input terminals respectively associated with one of said output terminals; a plurality of three or more NOR-type logic gates, each of said gates having its output connected to one of said output terminals and to an input of every other one of said logic gates; means for connecting each of said input terminals to an input of every logic gate other than the gate associated with the corresponding input and output terminals so that a select signal, applied to a selected input terminal, inhibits the operation of each gate other than the one connected to the output terminal associated with the selected input terminal, which associated gate is latched into an energized condition by said inhibited gates to energize the output terminal associated with the selected input terminal.
Claim 2
Dependent Claim
152 words
A logic latching circuit, comprising: a plurality of three or more output terminals; a plurality of three or more input terminals, each of said input terminals respectively associated with one of said output terminals; a plurality of three or more NOR-type logic gates, each of said gates having its output connected to one of said output terminals and to an input of every other one of said logic gates; means for connecting each of said input terminals to an input of every logic gate other than the gate associated with the corresponding input and output terminals so that a select signal, applied to a selected input terminal, inhibits the operation of each gate other than the one connected to the output terminal associated with the selected input terminal, which associated gate is latched into an energized condition by said inhibited gates to energize the output terminal associated with the selected input terminal.
Claim 3
Dependent Claim
106 words
An output selecting circuit comprising: a plurality of three or more input terminals; a plurality of three or more output terminals each respectively connected directly to one of said input terminals; and a plurality of three or more NOR-type logic gates, each of said gates having its output connected to an associated one of said output terminals and to an input of every other gate so that a select signal placed on a selected one of said input terminals is communicated to an input of each gate other than the one associated with the selected terminal thereby inhibiting the nonselected gates and their associated output terminals.
Claim 4
Dependent Claim
106 words
An output selecting circuit comprising: a plurality of three or more input terminals; a plurality of three or more output terminals each respectively connected directly to one of said input terminals; and a plurality of three or more NOR-type logic gates, each of said gates having its output connected to an associated one of said output terminals and to an input of every other gate so that a select signal placed on a selected one of said input terminals is communicated to an input of each gate other than the one associated with the selected terminal thereby inhibiting the nonselected gates and their associated output terminals.
Claim 5
Dependent Claim
144 words
An output selecting circuit comprising: a plurality of three or more input terminals; a plurality of three or more output terminals each respectively associated with one of said input terminals; and a plurality of three or more NOR-type logic gates, each of said gates having its output connected to an associated one of said output terminals and to an input of every other gate, each of said input terminals connected directly to an input of each logic gate other than the gate having its output connected to the output terminal associated with the corresponding input terminals so that a select signal placed upon a selected one of said input terminals inhibits the operation of each logic gate other than the one associated with the corresponding output terminal thereby inhibiting the nonselected gates and their associated output terminals while energizing the corresponding selected output terminal.
Claim 6
Dependent Claim
144 words
An output selecting circuit comprising: a plurality of three or more input terminals; a plurality of three or more output terminals each respectively associated with one of said input terminals; and a plurality of three or more NOR-type logic gates, each of said gates having its output connected to an associated one of said output terminals and to an input of every other gate, each of said input terminals connected directly to an input of each logic gate other than the gate having its output connected to the output terminal associated with the corresponding input terminals so that a select signal placed upon a selected one of said input terminals inhibits the operation of each logic gate other than the one associated with the corresponding output terminal thereby inhibiting the nonselected gates and their associated output terminals while energizing the corresponding selected output terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-24 | 1974-11-23 | 1975-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-24 | 1978-11-23 | 1979-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-24 | 1982-11-23 | 1983-05-25 | $7700.00 | Window Closed / Lapsed |