US3581016A
Expired / Lapsed
US
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Time-sharing telecommunication system
Assignee: Italtel SpA
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Filing: 1969-02-26
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Granted: 1971-05-25
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Expires: 1989-02-26
Abstract
Abstract A telephone exchange serving subscriber and trunk lines on a time-sharing basis has three circulating memories operating in synchronism, the operating cycle of each memory representing a frame of 100 phases or time slots serving for the registration of the number of a calling party in a phase of the first memory (100), the number of a called party in a corresponding phase of the second memory (200) and information on the progress of a call between the two parties in the same phase of the third memory (300). The second time slot (phase phi 2) of the second memory (200) is utilized as a binary counter successively registering, during consecutive frames, the addresses or call numbers of all lines served by the exchange. Each address thus inscribed is entered, one frame later, in a buffer register (800) for the duration of the following frame; concurrently, the line switches of the station identified by that address are briefly closed to sample the line voltage for the presence or absence of loop current. Special provisions are made for the calling of an outgoing trunk identified by a first digit ''''O'''' in its threedigit address. Other phases ( phi 1, phi 3, phi 4) at the beginning of each frame are utilized for the automatic checking of the equipment, with instant substitution of a standby memory (500) for the monitoring memory (300) or for any one of the three digital sections of either address memory (100, 200), designed as identical modules, if such module is found to be defective.
Inventors
- 👤 Saverio Martinelli
- 👤 Giorgio De Varda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:57
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
454 words
A telecommunication system comprising an exchange; a multiplicity of stations with lines terminating at said exchange; a transmission path common to all said lines; normally open individual switch means for each line closable during a phase of a multiphase frame for connecting the corresponding line to said transmission path whereby a communication channEl is established between two stations concurrently connected to said transmission path during respective phases of successive frames, the phases of each frame constituting at least one service phase and a multiplicity of communication phases; test means at said exchange for sequentially closing the switch means of consecutive lines during corresponding service phases of successive frames; voltage-detecting means operative during such service phase for ascertaining an active condition of a line thus tested; a circulating first address memory at said exchange responsive to said voltage-detecting means for temporarily storing an address of a calling station identified by said test means as associated with an active line in a recurring communication phase of successive frames; a circulating second address memory at said exchange; a circulating third memory at said exchange, all said memories having identical operating cycles each equal to a frame and a multiplicity of time slots corresponding to the phases thereof, said test means including counting means operative after each frame for progressively stepping a numerical lineidentifying code inscribed in a service time slot of one of said address memories whereby codes representing the addresses of all said lines successively appear during respective frames in the output of said one of said address memories; a register connected to said output for preserving, for the duration of one frame, the address inscribed in said service time slot during an immediately preceding frame; signal-responsive means at said exchange actuatable by selection signals arriving at said transmission path from said active line for entering the address of a called station in a communication time slot of said second memory coinciding with the communication time slot of said first memory occupied by the address of said calling station; circuit means under the control of said test means for determining the activities of the lines of said calling and called stations during the progress of a call and entering corresponding code words in a time slot of said third memory coinciding with the communication time slot of said first memory occupied by the address of said calling station, said third memory being provided with output circuitry controlling the entry and cancellation of said addresses in the communication time slots of said first and second memories; and operating means responsive to the outputs of said first and second memories for closing the switch means of lines identified by addresses stored thereon in the same communication time slot.
Claim 2
Dependent Claim
454 words
A telecommunication system comprising an exchange; a multiplicity of stations with lines terminating at said exchange; a transmission path common to all said lines; normally open individual switch means for each line closable during a phase of a multiphase frame for connecting the corresponding line to said transmission path whereby a communication channEl is established between two stations concurrently connected to said transmission path during respective phases of successive frames, the phases of each frame constituting at least one service phase and a multiplicity of communication phases; test means at said exchange for sequentially closing the switch means of consecutive lines during corresponding service phases of successive frames; voltage-detecting means operative during such service phase for ascertaining an active condition of a line thus tested; a circulating first address memory at said exchange responsive to said voltage-detecting means for temporarily storing an address of a calling station identified by said test means as associated with an active line in a recurring communication phase of successive frames; a circulating second address memory at said exchange; a circulating third memory at said exchange, all said memories having identical operating cycles each equal to a frame and a multiplicity of time slots corresponding to the phases thereof, said test means including counting means operative after each frame for progressively stepping a numerical lineidentifying code inscribed in a service time slot of one of said address memories whereby codes representing the addresses of all said lines successively appear during respective frames in the output of said one of said address memories; a register connected to said output for preserving, for the duration of one frame, the address inscribed in said service time slot during an immediately preceding frame; signal-responsive means at said exchange actuatable by selection signals arriving at said transmission path from said active line for entering the address of a called station in a communication time slot of said second memory coinciding with the communication time slot of said first memory occupied by the address of said calling station; circuit means under the control of said test means for determining the activities of the lines of said calling and called stations during the progress of a call and entering corresponding code words in a time slot of said third memory coinciding with the communication time slot of said first memory occupied by the address of said calling station, said third memory being provided with output circuitry controlling the entry and cancellation of said addresses in the communication time slots of said first and second memories; and operating means responsive to the outputs of said first and second memories for closing the switch means of lines identified by addresses stored thereon in the same communication time slot.
Claim 3
Dependent Claim
118 words
A system as defined in claim 1 wherein said first memory is provided with first input circuitry under the control of said output circuitry for entering an address stored in said register in an available communication time slot of said first memory, as determined by the absence of a code word in the corresponding time slot of said third memory, upon the ascertainment of an active condition on the line identified by the stored address; said second memory being provided with second input circuitry under the control of said signal-responsive means for entering a progressively varying count in a communication time slot thereof in response to dialing pulses arriving in the same time slot during successive operating cycles.
Claim 4
Dependent Claim
145 words
A system as defined in claim 2 wherein said first and second memories each consist of a plurality of parallel memory sections for accommodating respective digits of a multidigit address; said circuit means including an evaluation unit for recognizing a train of dialing pulses and emitting an end-of-digit signal upon the termination thereof; said second input circuitry including logical gate means responsive to said end-of-digit signal for directing successive trains of dialing pulses into different sections of said second memory and for controlling said circuit means to enter a waiting code in said third memory upon inscription of a digit in a last memory section; further comprising tone-genErating means under the control of said output circuitry for emitting a distinctive signal over said transmission path in the time slot occupied by the addresses of said calling and called stations in response to said waiting code.
Claim 5
Dependent Claim
140 words
A system as defined in claim 3, further comprising a busy-state indicator; first comparison means for detecting an identity between the contents of said register and an address appearing in the output of said first memory for actuating said busy-state indicator; second comparison means for detecting an identity between the contents of said register and an address appearing in the output of said second memory for controlling said circuit means to replace said waiting code in said third memory by a tentative-seizure code, and for actuating said busy-state indicator upon detection of an identity in the presence of a further code in said third memory means indicative of a more advanced state of a call involving said called station; said tone-generating means being responsive to the actuation of said busy-state indicator for emitting a busy signal over said transmission path.
Claim 6
Dependent Claim
179 words
A system as defined in claim 4 wherein said stations include local stations and terminals of trunk lines, said terminals having multidigit addresses characterized by an invariable first digit; further comprising repeating means at each of said terminals for retransmitting dialing pulses from said transmission path over the corresponding trunk line; said test means including trunk-identifying means operative during said service phase; said logical gate means being responsive to the inscription of said invariable first digit on a first section of said second memory for controlling said circuit means to enter said waiting code in said third memory prior to arrival of the next digit and for transferring the address of a trunk from said register to said communication time slot of said second memory in response to the operation of said trunk-identifying means in the presence of said waiting code on said third memory, thereby enabling said second comparison means to control said operating means for closing said switch means of the trunk line identified by said register for transmission of all further digits to said repeating means.
Claim 7
Dependent Claim
90 words
A system as defined in claim 1 wherein said exchange is provided with a plurality of substantially identical memory modules partly included in said first, second and third memories, said modules further including a standby module capable of being substituted for any active module in any of said memories; further comprising supervisory means for ascertaining a defective mode of operation of any active module and switchover means triggerable by said supervisory means for automatically substituting said standby module for an active module upon ascertainment of improper performance of the latter.
Claim 8
Dependent Claim
75 words
A system as defined in claim 6 wherein said supervisory means comprises a source of checking pulses coinciding with special service time slots of said memories, distributing means for simultaneously applying said checking pulses to corresponding inputs of a group of said active modules, and comparator means for detecting a mismatch in the outputs of the modules of said group; said switchover means comprising a logic matrix responsive to the output of said comparator means.
Claim 9
Dependent Claim
31 words
A system as defined in claim 7 wherein said group consists of three active modules, said comparator means comprising three comparators connected across respective subgroups of two of said active modules.
Claim 10
Dependent Claim
436 words
A telecommunication system comprising an exchange; a multiplicity of stations with lines terminating at said exchange; a transmission path common to all said lines; normally open individual switch means for each line momentarily closable during a phase of a multiphase frame for connecting the corresponding line to said transmission path whereby a communication channel is established between two stations concurrently connected to said transmission path during reSpective phases of successive frames; test means at said exchange for sequentially closing the switch means of consecutive lines during corresponding service phases of successive frames; voltage-detecting means operative during such service phase for ascertaining an active condition of a line thus tested; a first circulating memory at said exchange responsive to said voltage-detecting means for temporarily storing an address of a calling station identified by said test means as associated with an active line in a cyclically recurring communication time slot of successive operating cycles of said first memory coinciding with said frames, said test means including timer means for generating periodic pulses recurring at a predetermined cadence harmonically related to said operating cycles; a second circulating memory at said exchange having an operating cycle identical with that of said first memory and a number of time slots per cycle equaling that of said first memory and coinciding with the phases of a frame; signal-responsive means at said exchange actuatable by selection signals arriving at said transmission path from said active line for entering the address of a called station in a communication time slot of said second memory coinciding with the communication time slot of said first memory occupied by the address of said calling station; a third circulating memory at said exchange having an operating cycle and a number of time slots per cycle identical with those of said first and second memories; circuit means under the control of said test means for determining the activities of the lines of said calling and called stations during the progress of a call and entering corresponding code words in a time slot of said third memory coinciding with the communication time slot of said first memory occupied by the address of said calling station, said third memory being provided with output circuitry controlling the entry and cancellation of said addresses in the communication time slots of said first and second memories; operating means responsive to the outputs of said first and second memories for closing the switch means of lines identified by addresses stored thereon in the same communication time slot; and verification means connected to measure deviations of the recurrence rate of said periodic pulses from said cadence.
Claim 11
Dependent Claim
436 words
A telecommunication system comprising an exchange; a multiplicity of stations with lines terminating at said exchange; a transmission path common to all said lines; normally open individual switch means for each line momentarily closable during a phase of a multiphase frame for connecting the corresponding line to said transmission path whereby a communication channel is established between two stations concurrently connected to said transmission path during reSpective phases of successive frames; test means at said exchange for sequentially closing the switch means of consecutive lines during corresponding service phases of successive frames; voltage-detecting means operative during such service phase for ascertaining an active condition of a line thus tested; a first circulating memory at said exchange responsive to said voltage-detecting means for temporarily storing an address of a calling station identified by said test means as associated with an active line in a cyclically recurring communication time slot of successive operating cycles of said first memory coinciding with said frames, said test means including timer means for generating periodic pulses recurring at a predetermined cadence harmonically related to said operating cycles; a second circulating memory at said exchange having an operating cycle identical with that of said first memory and a number of time slots per cycle equaling that of said first memory and coinciding with the phases of a frame; signal-responsive means at said exchange actuatable by selection signals arriving at said transmission path from said active line for entering the address of a called station in a communication time slot of said second memory coinciding with the communication time slot of said first memory occupied by the address of said calling station; a third circulating memory at said exchange having an operating cycle and a number of time slots per cycle identical with those of said first and second memories; circuit means under the control of said test means for determining the activities of the lines of said calling and called stations during the progress of a call and entering corresponding code words in a time slot of said third memory coinciding with the communication time slot of said first memory occupied by the address of said calling station, said third memory being provided with output circuitry controlling the entry and cancellation of said addresses in the communication time slots of said first and second memories; operating means responsive to the outputs of said first and second memories for closing the switch means of lines identified by addresses stored thereon in the same communication time slot; and verification means connected to measure deviations of the recurrence rate of said periodic pulses from said cadence.
Claim 12
Dependent Claim
58 words
A system as defined in claim 9 wherein said timer means comprises a source of clock pulses of a fundamental recurrence frequency and frequency-divider means for generating said cadence as an aliquot fraction of 1/n of said fundamental frequency, said verification means including a time-constant network establishing a tolerance range between 1/(n-1) and 1/(n+1) of said fundamental frequency.
Claim 13
Dependent Claim
18 words
A system as defined in claim 10 wherein said time-constant network comprises a pair of cascaded monostable multivibrators.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-24 | 1974-11-23 | 1975-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-24 | 1978-11-23 | 1979-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-24 | 1982-11-23 | 1983-05-25 | $7700.00 | Window Closed / Lapsed |