Decimal to binary conversion

Claim 3

A circuit for converting a binary coded decimal (BCD) number representing a multiple digit decimal number of a binary number comprising, in combination: register means having a plurality of storage stages Bn, Bn 1, Bn 2, Bn 3, Bn 4......B1, B0, B 1, B 2, in decreasing order of significance, each stage having a shift terminal, signal input terminal means and signal output terminal means, each stage except the Bn 2 and B 2 stages being connecTed at its output terminal means to the input terminal means of the stage of next lower significance for shifting the bit stored therein to said stage of next lower significance in response to a shift pulse applied to its shift terminal; means for inserting into the most significant four stages Bn....Bn 3 of said register, during successive time intervals, the successive 4-bit BCD numbers which define said multiple digit decimal number, starting with the most significant decimal digit; adder means connected to the output terminal means of the Bn 2, B0 and B 2 stages of said register means for adding, in response to each shift pulse, the bits stored in these stages to any carry produced in response to the preceding shift pulse, for producing a sum signal and applying it to the input terminal means of said Bn 3 stage, and for producing and storing a carry; and means responsive to each insertion into said register means of four bits of a BCD number, for applying a group of time sequential shift pulses to the shift terminals of all stages of said register means and to said adder means, of sufficient number to shift the least significant bit of said BCD number from said Bn 3 stage to said B0 stage of said register means and for causing said adder means to perform a number of sequential additions equal to the number of said shift pulses in said group.

Claim 4

A circuit for converting a binary coded decimal (BCD) number representing a multiple digit decimal number of a binary number comprising, in combination: register means having a plurality of storage stages Bn, Bn 1, Bn 2, Bn 3, Bn 4......B1, B0, B 1, B 2, in decreasing order of significance, each stage having a shift terminal, signal input terminal means and signal output terminal means, each stage except the Bn 2 and B 2 stages being connecTed at its output terminal means to the input terminal means of the stage of next lower significance for shifting the bit stored therein to said stage of next lower significance in response to a shift pulse applied to its shift terminal; means for inserting into the most significant four stages Bn....Bn 3 of said register, during successive time intervals, the successive 4-bit BCD numbers which define said multiple digit decimal number, starting with the most significant decimal digit; adder means connected to the output terminal means of the Bn 2, B0 and B 2 stages of said register means for adding, in response to each shift pulse, the bits stored in these stages to any carry produced in response to the preceding shift pulse, for producing a sum signal and applying it to the input terminal means of said Bn 3 stage, and for producing and storing a carry; and means responsive to each insertion into said register means of four bits of a BCD number, for applying a group of time sequential shift pulses to the shift terminals of all stages of said register means and to said adder means, of sufficient number to shift the least significant bit of said BCD number from said Bn 3 stage to said B0 stage of said register means and for causing said adder means to perform a number of sequential additions equal to the number of said shift pulses in said group.

Claim 5

A circuit as set forth in claim 2, wherein said means for inserting comprises a keyboard.

Claim 6

In a system for converting a decimal number into an equivalent binary number by shifting the binary digits already converted to obtain even multiples thereof to be added together to derive the tens multiple of the binary number to be added to the decimal digit being entered, the improvement comprising: adder means having input terminal means for signals representing three bits to be added and an output terminal means for producing a manifestation of a sum; and binary register means storing said binary number and the binary equivalent of said decimal digit coupled at three stages thereof to said three input means, respectively, of said adder means, and coupled at another stage to said output terminal means of said adder means, and coupled at another stage to said output terminal means of said adder means for receiving said manifestation of a sum, said binary register means including also additional stages preceeding and following the stages containing the binary number for rendering unnecessary any preliminary shifts to obtain said even multiples of said binary number.

Claim 7

In a system for converting a decimal number into an equivalent binary number by shifting the binary digits already converted to obtain even multiples thereof to be added together to derive the tens multiple of the binary number to be added to the decimal digit being entered, the improvement comprising: adder means having input terminal means for signals representing three bits to be added and an output terminal means for producing a manifestation of a sum; and binary register means storing said binary number and the binary equivalent of said decimal digit coupled at three stages thereof to said three input means, respectively, of said adder means, and coupled at another stage to said output terminal means of said adder means, and coupled at another stage to said output terminal means of said adder means for receiving said manifestation of a sum, said binary register means including also additional stages preceeding and following the stages containing the binary number for rendering unnecessary any preliminary shifts to obtain said even multiples of said binary number.