Multiple mode frequency divider circuit

Claim 3

individually selectively tapping said first array at first and second locations thereon, A. selecting said first and second locations to determine two output pulse frequencies;

Claim 4

individually selectively tapping said first array at first and second locations thereon, A. selecting said first and second locations to determine two output pulse frequencies;

Claim 5

The method of claim 1, tapping said second array at a second location thereon, selecting said second location to determine a second output pulse repetition rate, and wherein said step of feeding signals from said at least one location comprises feeding signals from a selected one of said first and second locations to said control means to additionally deactivate said selected one of said first and second locations on said second array and to activate the other of said first and second locations on said second array.

Claim 6

The method of claim 1, and bringing all the flip-flops to a known initial condition prior to said step of feeding pulses from the pulse source to said input end of said first array.

Claim 7

feeding signals from a selected one of said first and second locations to A. an output line, B. the input end of a second array of flip-flops arranged in cascade, and C. to means to reset said first array;

Claim 8

feeding signals from a selected one of said first and second locations to A. an output line, B. the input end of a second array of flip-flops arranged in cascade, and C. to means to reset said first array;

Claim 9

individually selectively tapping said second array at at least one location thereon, A. selecting said at least one location to determine at least one output pulse repetition rate;

Claim 10

individually selectively tapping said second array at at least one location thereon, A. selecting said at least one location to determine at least one output pulse repetition rate;

Claim 11

A frequency divider circuit comprising clock means adapted to produce pulses at a constant predetermined rate, first and second arrays of flip-flops each arranged in cascade, means to feed the clock means pulses to the input end of said first cascaded array, first and second sets of contacts connected in parallel circuit to each of the outputs of each of the flip-flops of said first cascaded array, at least one set of contacts connected in parallel circuit to each of the outputs of each of the flip-flops of said second cascaded array, a moveable member associated with each of said sets of contacts and adapted to cooperate with any one contact only of its associated set, an output line, control means interconnecting all of said moveable members, said output line, and the input end of said second cascaded array, said control means comprising means to selectively enable one moveable member of the pair of moveable members cooperable with said first and second sets of contacts on said first cascaded array, said control means comprising means to feed signals from said selected moveable member to said output line and to the input end of said second cascaded array, said control means comprising means to feed signals from the moveable member associated with said at least one set of contacts on said second cascaded array to said means to selectively enable a moveable member to cause said means to selectively enable a moveable member to cause said means to selectively enable a moveable member to switch from one to the other as to the selected one of the pair of moveable members enabled thereby.

Claim 12

A frequency divider circuit comprising clock means adapted to produce pulses at a constant predetermined rate, first and second arrays of flip-flops each arranged in cascade, means to feed the clock means pulses to the input end of said first cascaded array, first and second sets of contacts connected in parallel circuit to each of the outputs of each of the flip-flops of said first cascaded array, at least one set of contacts connected in parallel circuit to each of the outputs of each of the flip-flops of said second cascaded array, a moveable member associated with each of said sets of contacts and adapted to cooperate with any one contact only of its associated set, an output line, control means interconnecting all of said moveable members, said output line, and the input end of said second cascaded array, said control means comprising means to selectively enable one moveable member of the pair of moveable members cooperable with said first and second sets of contacts on said first cascaded array, said control means comprising means to feed signals from said selected moveable member to said output line and to the input end of said second cascaded array, said control means comprising means to feed signals from the moveable member associated with said at least one set of contacts on said second cascaded array to said means to selectively enable a moveable member to cause said means to selectively enable a moveable member to cause said means to selectively enable a moveable member to switch from one to the other as to the selected one of the pair of moveable members enabled thereby.

Claim 13

feeding signals from said at least one location on said second array to control means to A. deactivate said selected one of said first and second locations on said first array and to activate the other of said first and second locations on said first array, and B. reset said second array.

Claim 14

feeding signals from said at least one location on said second array to control means to A. deactivate said selected one of said first and second locations on said first array and to activate the other of said first and second locations on said first array, and B. reset said second array.

Claim 15

The circuit of claim 4, a second set of contacts respectively connected in parallel circuit to the contacts of said at least one set of contacts on said second cascaded array and a moveable member associated therewith, said control means comprising second means to selectively enable one moveable member of the pair of moveable members cooperable with said first and second sets of contacts on said second cascaded array, and said control means comprising means to feed signals from said selected moveable member associated with said second cascaded array to both of said means to selectively enable a moveable member to cause both said means to selectively enable a moveable member to from one to the other, as to the selected one of the pair of moveable members enabled thereby.

Claim 16

The circuit of claim 5, said first and second means to selectively enable a moveable member comprising first and second control flip-flops respectively.

Claim 17

The circuit of claim 6, grounding switch means associated with said first control flip-flop to prevent said first control flip-flop from switching from one to the other as to the selected one of the pair of moveable members enabled thereby.

Claim 18

The circuit of claim 6, grounding switch means associated with said first control flip-flop to permit said first control flip-flop to make one switch only from one to the other and thereafter to prevent said first control flip-flop from switching from one to the other as to the selected one of the pair of moveable members enabled thereby.

Claim 19

The circuit of claim 6, grounding switch means associated with said second control fliP-flop to prevent said second control flip-flop from switching from one to the other as to the selected one of the pair of moveable members enabled thereby.

Claim 20

The circuit of claim 4, and grounding switch means for each of said first and second cascaded arrays, whereby all of said flip-flops may be brought to a known initial condition by operation of said grounding switch means prior to feeding the first clock means pulse to the input end of said first cascaded array.