Automatic equalizer for digital data transmission systems

Claim 3

The invention as set forth in claim 1 including means for reading the bits of each of said words in said first and second storage means out successively into said processing means during each of said successive intervals.

Claim 4

The invention as set forth in claim 2 including means operative during each of said intervals for replacing digital words representing signals transmitted during such intervals each in consecutively spaced locations in said first storage means, said second words being disposed in the same order in consecutively spaced locations in said second storage means, means for reading said second words out of said second storage means in sequence corresponding to the order of their storage therein during each of said intervals, and means for reading said first words out of said first storage means in sequence corresponding to the order of their storage therein starting with successively higher order ones of said first words during successive ones of said intervals.

Claim 5

The invention as set forth in claim 3 wherein said first and second storage means each includes a plurality of memory elements, the elements in said first storage means being in Corresponding relationship to the memory elements in said second storage means, each element having storage for a different bit of said words.

Claim 8

The invention as set forth in claim 5 wherein said signals which are transmitted over said channel are analog signals and including analog-to-digital converting means operative at said successive times for converting said analog signals into said data words at each of said successive times.

Claim 9

The invention as set forth in claim 6 wherein means are provided for reading out said plurality of stored data words and weight words into said accumulating means serially bit-by-bit at least once during each of said successive times, whereby to provide successive ones of said sum words at least once during each of said successive times.

Claim 10

The invention as set forth in claim 7 including means for operating said correlation means at least once during each of said successive times, and wherein means are included in said correlation means for providing said outputs when the magnitude of the sum of consecutive correlations over a predetermined number of said successive times exceeds a certain number.

Claim 11

The invention as set forth in claim 8 including means for operating said means for adjusting said one weight word at least once during each of said successive times in response to said correlation means outputs for incrementally adjusting said one weight word.

Claim 12

The invention as set forth in claim 9 wherein means are provided for determining the sign of said one data word and applying an output representing said sign to said correlation means.

Claim 13

The invention as set forth in claim 10 including means operative to provide said sign of successive ones of said data words each for a predetermined number of said successive times, and means for operating said weight word-adjusting means to adjust said weight words which correspond to each of said successive data words, each during said predetermined number of successive times.

Claim 14

The invention as set forth in claim 5 including distortion detection means responsive to each occurrence of said sum word representing a predetermined value for providing upon occurrence of a predetermined number of sum words having said values during a given period of time an output indicating distortion in said system.

Claim 15

An adaptive equalizer which comprises: a. a signal memory having storage for a plurality of multibit data words; b. a weight memory having storage for a like plurality of multibit weight words each corresponding to a different one of said data words; c. a serial accumulator coupled to read out lines from said signal memory and weight memory for accumulating a sum word equal to the sum of the products of said corresponding weight words and data words; d. digital logic coupled to the output of said accumulator for decoding said sum word into output bits of opposite value to each other depending on the sense of the error in said sum wOrd; e. a code generator for providing output codes representing different ones of said weight words; f. a data word sign detector coupled to the readout line from said signal memory and operated by said code generator for providing output bits of opposite value to each other depending upon the sign of the data word corresponding to the weight word represented by the code produced by said generator; g. a correlator including a multiplier and an accumulator, said multiplier being input coupled to said logic which produces said error sense bits and to said data word sign detector, said accumulator having overflow and underflow outputs for producing overflow bits upon occurrence of a predetermined magnitude of the sum of consecutive data word sign detector and error sense output bit products and underflow output bits upon occurrence of the negative of said magnitude; h. a serial adder coupled to the readout line of said weight memory and to said overflow and underflow outputs, the output of said adder being coupled to the write input of said weight memory; and i. means operated by said code generator for reading out bits of the weight word corresponding to said code into said last-named serial adder, whereby said weight word is incrementally adjusted and written back into said weight memory.

Claim 16

An adaptive equalizer which comprises: a. a signal memory having storage for a plurality of multibit data words; b. a weight memory having storage for a like plurality of multibit weight words each corresponding to a different one of said data words; c. a serial accumulator coupled to read out lines from said signal memory and weight memory for accumulating a sum word equal to the sum of the products of said corresponding weight words and data words; d. digital logic coupled to the output of said accumulator for decoding said sum word into output bits of opposite value to each other depending on the sense of the error in said sum wOrd; e. a code generator for providing output codes representing different ones of said weight words; f. a data word sign detector coupled to the readout line from said signal memory and operated by said code generator for providing output bits of opposite value to each other depending upon the sign of the data word corresponding to the weight word represented by the code produced by said generator; g. a correlator including a multiplier and an accumulator, said multiplier being input coupled to said logic which produces said error sense bits and to said data word sign detector, said accumulator having overflow and underflow outputs for producing overflow bits upon occurrence of a predetermined magnitude of the sum of consecutive data word sign detector and error sense output bit products and underflow output bits upon occurrence of the negative of said magnitude; h. a serial adder coupled to the readout line of said weight memory and to said overflow and underflow outputs, the output of said adder being coupled to the write input of said weight memory; and i. means operated by said code generator for reading out bits of the weight word corresponding to said code into said last-named serial adder, whereby said weight word is incrementally adjusted and written back into said weight memory.

Claim 17

The invention as set forth in claim 13 including a timing unit for providing timing pulses for addressing said memories, operating said accumulators and said digital logic and said data word sign detector on a serial bit-by-bit basis.

Claim 18

The invention as set forth in claim 13 wherein said first-named accumulator includes a serial adder, a register for accumulating said sum words, and logic means for providing to the input of said first-named accumulator the 2''s complement of the most significant bit of each weight word having a negative sign.

Claim 19

The invention as set forth in claim 13 wherein said timing unit includes a plurality of counters, a first of said counters being a product timer for providing a sequence of timing pulses one more in number than the number of bits in the product of one of said data words with one of said weight words, a second of said counters being operated by one of said product timing pulses for producing a plurality of timing pulses each corresponding to a different bit of each of said weight words, a third counter, means for starting said third counter upon coincidence of one of said product timing pulses and successive ones of said weight bit timing pulses such that said third counter provides a plurality of successive timing pulses, one for each bit of each of said data words, address lines for the bits of said signal memory being coupled to the outputs of said third counter, address lines for the bits of said weight memory being coupled to the outputs of said second counter, whereby each said data word is read and shifted in time with respect to said product timer during readout of each bit of said weight word into said accumulator.

Claim 20

The invention as set forth in claim 13 including a fourth counter and a fifth counter, means for applying pulses to said counters at successive time intervals corresponding to the time for read out of an entire data word from said signal memory into said first-named accumulator, said fifth counter having at least one additional state than said fourth counter, means for providing timing pulses corresponding to successive ones of said data words from said fourth counter and for successive ones of said weight words said fifth counter, means for providing an additional timing pulse from said fifth counter upon occurrence of said additional state thereof, and means included in said error sense decoding logic, said data word sign detector and said serial adder for adjusting said weight words operative in response to said additional timing pulse.

Claim 21

The invention as set forth in claim 13 including an analog-to-digital converter for translating input analog signals to said equalizer intO data words for storage in successive word locations in said signal memory once during successive intervals.

Claim 22

The invention as set forth in claim 18 including a symbol detector coupled to the output of said first-named serial accumulator for decoding the sum words stored therein into equalized output bits representing the data represented by successive ones of said input analog signals.

Claim 23

The invention as set forth in claim 19 wherein said input analog signal is a multilevel data signal which during a preamble has fewer levels than during normal transmission, and wherein said error sense decoding logic includes means for converting said logic to respond to errors in said fewer level signals during said preamble.

Claim 24

The invention as set forth in claim 19 wherein said error sense decoding logic and said symbol detector include a plurality of flip-flops, means for transferring the most significant of the bits stored in said first serial accumulator register for storage in said flip-flops, and a plurality of digital gates for decoding the data stored in said flip-flops to provide the bits of said equalized data bits and the bits representing the sense of said error.