Parabolic waveform generating circuit

Claim 2

A circuit for generating a parabolic voltage comprising: a. a first current source for producing a constant current, b. a second current source for producing a sawtooth current having a mean vAlue equal to the value of said constant current, c. means for connecting said first and second current sources in a serial configuration, and d. an integrating capacitor coupled to the junction of said first and second current sources having current applied thereto equal to the difference between said constant and sawtooth currents for linearly charging and discharging said capacitor during each sawtooth period, whereby a parabolic voltage is generated across said capacitor.

Claim 3

A circuit as in claim 1 having a balanced configuration with the mean voltage of said junction equal to a given reference level and said capacitor connected between said junction and a point fixed to said reference level.

Claim 4

A circuit as in claim 2 which includes switching means connected across said capacitor synchronously operated to be normally open and to instantaneously close at the end of each parabolic waveform, thereby shorting said capacitor to said reference level at times when the capacitor current is optimumly at zero.

Claim 5

A circuit as in claim 3 wherein: a. said first current source includes a first high current gain transistor connected as an emitter follower, b. a constant voltage coupled to the base of said first transitor for providing said constant current as proportional thereto, c. said second current source includes a second emitter follower connected high current gain transistor of complementary type of said first transistor, and d. a sawtooth voltage coupled to the base of said second transistor for providing said sawtooth current as proportional thereto.

Claim 6

A circuit as in claim 4 wherein: a. said first and second transistors are a complementary PNP-NPN pair, b. a first DC bias source is coupled through a first emitter resistance to the emitter of said first transistor and through a first resistive voltage divider circuit to said reference level, a tap on said voltage divider being connected to the base of said first transistor, c. a second DC bias source of opposite polarity to said first source is coupled through a second emitter resistance to the emitter of said second transistor and through a second resistive voltage divider circuit to a sawtooth voltage source, a tap of said voltage divider being connected to the base of said second transistor, and d. the collectors of said first and second transistors being connected to said junction.