Solid-state storage device

Claim 2

The combination claimed in claim 2 wherein said means for establishing said charge carrier path includes a gate electrode disposed adjacent to and in physical contact with at least part of said charge carrier storing Means whereby a bias potential can be applied to electrically establish said charge carrier path.

Claim 3

The combination claimed in claim 1 wherein said charge carrier storing means includes a first layer of insulating material having a first surface disposed adjacent to and in physical contact with said surface of said substrate and a second layer of insulating material having a first surface disposed adjacent to and in physical contact with at least a portion of a second surface of said first layer of insulating material, said second layer having trap means for trapping and storing charge carriers.

Claim 4

The combination claimed in claim 4 wherein said trap means comprise structural defects in said second layer.

Claim 5

The combination claimed in claim 2 wherein said source region and said drain region are of N-type conductivity and said charge carriers are electrons.

Claim 6

The combination claimed in claim 2, wherein said source region and said drain region are of P-type conductivity and said charge carriers are holes.

Claim 7

A solid- state storage device comprising: a. a semiconductor substrate having spaced source and drain regions disposed within and adjacent a common surface of said substrate; b. a first layer of insulating material having a first surface disposed adjacent to and in physical contact with said common surface of said substrate, the interface between said substrate and said first insulating layer defining a Schottky barrier; c. a first gate disposed adjacent to and in physical contact with a part of a second surface of said first insulating layer, said gate being electrically insulated from said substrate; d. first means for applying a bias potential to said first gate for creating a channel in said substrate between said source region and said drain region whereby charge carriers are caused to flow therethrough; e. a second layer of insulating material having a first surface disposed adjacent to and in physical contact with another part of said second surface of said first insulating layer and further disposed so as to insulate said first gate, said second insulating layer having trap means distributed therein for trapping certain of said charge carriers; f. a second gate disposed adjacent to and in physical contact with a second surface of said second layer and further disposed to overlap at least part of said channel so as to facilitate the establishment of a depletion region within said channel; g. second means for applying a potential to said drain region so as to establish a depletion region within said part of said channel overlapped by said second gate; and h. third means for applying an accelerating potential to said second gate for accelerating said certain charge carriers from said channel over said Schottky barrier and into said trap means.

Claim 8

The combination claimed in claim 8 wherein said semiconductor substrate is silicon.

Claim 9

The combination claimed in claim 8 wherein said first insulating material is silicon dioxide (SiO2).

Claim 10

The combination of claim 8 wherein said second insulating material is silicon nitride (Si3N4).

Claim 11

The combination claimed in claim 8 wherein said first gate is metallic.

Claim 12

The combination claimed in claim 8 wherein said second gate is metallic.

Claim 13

The combination claimed in claim 8 wherein said source region and said drain region are of N-type conductivity and said charge carriers are electrons.

Claim 14

The combination claimed in claim 8 wherein said source region and said drain region are of P-type conductivity and said charge carriers are holes.

Claim 15

The combination claimed in claim 8 wherein said second gate overlaps the part of said drain region and part of said channel.

Claim 16

The combination claimed in claim 8 wherein said first gate overlaps part of said source region and part of said channel.

Claim 17

The combination claimed in claim 17 wherein said second gate overlaps said drain region and saiD first gate whereby said channel is completely overlapped by the combination of said first and second gates.

Claim 18

A solid-state storage device comprising: a. a semiconductor substrate having spaced source and drain regions disposed within and adjacent a common surface of said substrate; b. a first layer of insulating material having a first surface disposed adjacent to and in physical contact with said common surface of said substrate, the interface between said substrate and said first insulating layer defining a Schottky barrier; c. a second layer of insulating material having a first surface disposed adjacent to and in physical contact with a second surface of first insulating layer, and having trap means distributed therein for trapping charge carriers emanating from said source region; d. a first gate disposed adjacent to and in physical contact with a part of second surface of said second insulating layer, said hate being electrically insulated from said substrate; e. first means for applying a bias potential to said first gate for creating a channel in said substrate between said source region and said drain region whereby said charge carriers emanating from said source region are caused to flow therethrough; f. a third layer of insulating material having a first surface disposed adjacent to and in physical contact with another part of said second surface of said second insulating later and further disposed so as to insulate said first gate; g. a second gate disposed adjacent to and in physical contact with a second surface of said third layer and further disposed to overlap at least part of said channel so as to facilitate the establishment of a depletion region within said channel; h. second means for applying a potential to said drain region so as to establish a depletion region within said part of said channel overlapped by said second gate; and i. third means for applying an accelerating potential to said second gate for accelerating certain of said charge carriers from said channel over said Schottky barrier and into said trap means.

Claim 19

The combination claimed in claim 19 wherein said semiconductor substrate is silicon.

Claim 20

The combination claimed in claim 19 wherein said first insulating material is silicon dioxide (SiO2).

Claim 21

The combination claimed in claim 19 wherein said second insulating material is silicon nitride (Si3N4 ).

Claim 22

The combination claimed in claim 19 wherein said third insulating material is silicon nitride (Si3N4).

Claim 23

The combination claimed in claim 19 wherein said first gate is metallic.

Claim 24

The combination claimed in claim 19 wherein said second gate is metallic.

Claim 25

The combination claimed in claim 19 wherein said source region and said drain region are of N-type conductivity and said charge carriers are electrons.

Claim 26

The combination claimed in claim 19 wherein said source region and said drain region are of P-type conductivity and said charge carriers are holes. 28 The combination claimed in claim 19 wherein said second gate overlaps part of said drain region and part of said channel.

Claim 27

The combination claimed in claim 19, wherein said first gate overlaps part of said source region and part of said channel.

Claim 28

The combination claimed in claim 19, wherein said second gate overlaps said drain region and said first gate whereby said channel is completely overlapped by the combination of said first and second gates.