Binary to decimal tree relay decoder circuit with memory display

Claim 1

In a translating circuit for converting binary signals to decimal signals, in combination: 1. a plurality of input conductors for receiving a combination of binary signals corresponding to a binary number; 2. a plurality of output conductors for receiving the output of said circuit on one of said output conductors in the form of a decimal signal corresponding to said binary number; 3. a plurality of latching relays having associated sets of latching and unlatching coils and singular and plural groups of arm members arranged in a tree relay grouping for the establishment of a selected conducting path to a selected said output conductor, said unlatching coils when energized being operative to unlatch said arms within a predetermined short time period; 4. a control nonlatching relay having an operating coil and an associated set of normally open contacts and a set of normally closed contacts, said operating coil when energized being operative after said short time period and within a longer brief time period to close said normally open and to open said normally closed contacts; 5. external control means having an associated set of master control contacts; and 6. an operating source of potential; said binary input and decimal output conductors, said latching and unlatching coils, said control relay normally open and normally closed contacts, said master control contact and said source of potential being connected such that upon the impression of a selected combination of binary signals on said input conductors and the closing of said master contact, said control relay operating coil is energized, said unlatching coils are all caused to be simultaneously energized through said normally closed contacts and said arms are all unlatched from their immediately prior positions and are brought to positions within said short time period effective to establish a first conducting path through said arms and to produce an operating potential on that output conductor corresponding to decimal zero, following said short time period but within said longer brief period those said latching coils which are connected to the respective said binary input conductors on which the said binary signals are impressed are caused to be energized while the remaining said latching coils remain deenergized and the said arms are brought to positions effective to establish a second conducting path through said arms and to produce an operating potential on that output decimal conductor corresponding in decimal notation to the said binary signal combination and such that following opening of said master contact after establishment of said second path said normally oPen and normally closed contacts are restored to their respective normal positions while said arms maintain said second path and the operating potential produce thereon, said translating circuit thereby exhibiting the capability of holding the last decimal signal on said second path so long as said master contact remains open and independent of new binary signal combinations being impressed, removed or changed on said input conductors and upon a further closing of said master contact being adapted to repeat said sequence of going to decimal zero prior to establishment of a new decimal signal.