Decoding arrangement for binary code decimal groups

Claim 2

Decoder, particularly for decimal-grouped four-digit binary codes with four input lines corresponding to the binary positions for the parallel feeding of the signals to be decoded, and with ten outputs corresponding to the decimal digits for emitting the decoded signals, where the binary code contains characters of a first type which are already clearly associated with a decimal digit by identical symbols for some of the binary positions, while the other characters of the binary code are characters of a second type, which would not yet permit a clear association with decimal digits in the case of identical symbols for the remaining binary positions, the improvement comprising 10 logic elements of the NOR-NAND type associated with the binary positions whose outputs correspond to the decoded decimal positions, the inputs of the logic elements associated with the binary characters of the first type being connected with those input lines of the decoder whose associated binary positions suffice for the definite association with decimal digits in the case of identical symbols, a portion of the inputs of one logic element associated with a binary character of the second type being connected with input lines of the decoder while the remaining inputs to said one logic element are connected to outputs of other logic elements, said other logic elements being selected such that they are connected with at least a portion of their inputs with decoder input lines which are the same as those input lines connected with the first inputs of said one logic element.

Claim 3

A decoder as defined in claim 1 wherein said logic elements are NAND gates.

Claim 4

Decoder, particularly for decimal-grouped four-digit binary codes with four input lines corresponding to the binary positions for the parallel feeding of the signals to be decoded, and with 10 outputs corresponding to the decimal digits for emitting the decoded signals, where the binary code contains characters of a first type which are already clearly associated with a decimal digit by identical symbols for some of the binary positions, while the other characters of the binary code are characters of a second type, which would not yet permit a clear association with decimal digits in the case of identical symbols for the remaining binary positions, the improvement comprising 10 logic elements of the NOR-NAND type associated with the binary positions whose outputs correspond to the decoded decimal positions, the inputs of the logic elements associated with the binary characters of the first type being connected to two input lines of the decoder whose associated binary positions suffice for the definite association with decimal digits in the case of identical symbols, a portion of the inputs of one logic element associated with a binary character of the second type being connected with one input line of the decoder while the remaining inputs to said one logic element are connected to outputs of other logic elements, said other logic elements being selected such that they are connected with the decoder input line which is the same as the decoder input line connected with the first input of said one logic element.

Claim 5

Decoder, particularly for decimal-grouped four-digit binary codes with four input lines corresponding to the binary positions for the parallel feeding of the signals to be decoded, and with 10 outputs corresponding to the decimal digits for emitting the decoded signals, where the binary code contains characters of a first type which are already clearly associated with a decimal digit by identical symbols for some of the binary positions, while the other characters of the binary code are characters of a second type, which would not yet permit a clear association with decimal digits in the case of identical symbols for the remaining binary positions, the improvement comprising 10 logic elements of the NOR-NAND type associated with the binary positions whose outputs correspond to the decoded decimal positions, the inputs of the logic elements associated with the binary characters of the first type being connected to two input lines of the decoder whose associated binary positions suffice for the definite association with decimal digits in the case of identical symbols, a portion of the inputs of one logic element associated with a binary character of the second type being connected with one input line of the decoder while the remaining inputs to said one logic element are connected to outputs of other logic elements, said other logic elements being selected such that they are connected with the decoder input line which is the same as the decoder input line connected with the first input of said one logic element.

Claim 6

Decoder, particularly for decimal-grouped four-digit binary codes with four input lines corresponding to the binary positions for the parallel feeding of the signals to be dEcoded, and with 10 outputs corresponding to the decimal digits for emitting the decoded signals, where the binary code contains characters of a first type which are already clearly associated with a decimal digit by identical symbols for some of the binary positions, while the other characters of the binary code are characters of a second type, which would not yet permit a clear association with decimal digits in the case of identical symbols for the remaining binary positions, the improvement comprising 10 logic elements of the NOR-NAND type associated with the binary positions whose outputs correspond to the decoded decimal positions, the inputs of the logic elements associated with the binary characters of the first type being connected with at least two input lines of the decoder whose associated binary positions suffice for the definite association with decimal digits in the case of identical symbols, a portion of the inputs of one logic element associated with a binary character of the second type being connected with at least one input line of the decoder while the remaining inputs to said one logic element are connected to outputs of other logic elements, said other logic elements being selected such that they are connected with at least one decoder input line which is the same as the at least one decoder input line connected with the first inputs of said one logic element.

Claim 7

Decoder, particularly for decimal-grouped four-digit binary codes with four input lines corresponding to the binary positions for the parallel feeding of the signals to be dEcoded, and with 10 outputs corresponding to the decimal digits for emitting the decoded signals, where the binary code contains characters of a first type which are already clearly associated with a decimal digit by identical symbols for some of the binary positions, while the other characters of the binary code are characters of a second type, which would not yet permit a clear association with decimal digits in the case of identical symbols for the remaining binary positions, the improvement comprising 10 logic elements of the NOR-NAND type associated with the binary positions whose outputs correspond to the decoded decimal positions, the inputs of the logic elements associated with the binary characters of the first type being connected with at least two input lines of the decoder whose associated binary positions suffice for the definite association with decimal digits in the case of identical symbols, a portion of the inputs of one logic element associated with a binary character of the second type being connected with at least one input line of the decoder while the remaining inputs to said one logic element are connected to outputs of other logic elements, said other logic elements being selected such that they are connected with at least one decoder input line which is the same as the at least one decoder input line connected with the first inputs of said one logic element.