Priority circuit

Claim 2

A circuit for granting priority to one of n request for service signals of different priorities, where n is an integer greater than 1, comprising, in combination: n lines, each for a different request for service signal; an n stage register, each stage coupled to a different line; means responsive to the presence of a request for service signal on a line for setting the register stage coupled to that line to thereby store that signal; means responsive to any set stage of said register for disconnecting all of said lines from said register; means responsive to any set stage in said register which is storing a request for service signal of given priority for resetting any other stage in the register which is storing a request for service signal of lower priority; and said means for disconnecting all of said lines from said register including a plurality of input gates, one for each register stage, each connected between a line and its register stage, and means responsive to any set stage of said register for disablIng all of said input gates.

Claim 3

A circuit as set forth in claim 1, wherein each stage of the register includes a reset terminal and wherein said means for resetting any other stage of claim 1 includes: gates connected to said reset terminals; means responsive to a set stage of said register for priming a gate connected to a reset terminal, at each stage for storing a request for service signal of lower priority than said set stage of said register; and means, including delay means, responsive to a set stage of a register for enabling said primed gates and thereby causing said gates to apply reset signals to their respective stages.

Claim 4

A circuit for granting priority to one of n request for service signals of different priorities, where n is an integer greater than 1, comprising, in combination: n lines, each for a different request for service signal; an n stage register, each stage comprising a flip-flop having a set and a reset terminal, each stage for storing a signal of different priority; n normally primed gates coupling said n input lines to the respective set terminals of said flip-flops, whereby in response to the presence of a request for service signal on any line, the input gate to that line becomes enabled and applies a set signal to its flip-flop; n-1 reset gate means, each such means including at least one reset gate, one reset gate means for each flip-flop other than the flip-flop for storing the request for service signal of highest priority, each such gate means coupled to the reset terminal of a different flip-flop; means responsive to any set flip-flop of said register for priming a reset gate for each flip-flop of said register for storing a signal of lower priority than said set flip-flop; means responsive to any set flip-flop of said register for producing a disabling signal after a first delay interval Delta t1 and applying it to all input gates to said set terminals of said flip-flops; and means responsive to said disabling signal for producing a reset signal after an additional delay interval Delta t2 and for applying that reset signal to all of said reset gate means, whereby when there is more than one flip-flop which is set, all except one of these flip-flops become reset, the flip-flop remaining set being the one storing the request for service signal of highest priority in the more than one previously set flip-flops.

Claim 5

A circuit for granting priority to one of n request for service signals of different priorities, where n is an integer greater than 1, comprising, in combination: n lines, each for a different request for service signal; an n stage register, each stage comprising a flip-flop having a set and a reset terminal, each stage for storing a signal of different priority; n normally primed gates coupling said n input lines to the respective set terminals of said flip-flops, whereby in response to the presence of a request for service signal on any line, the input gate to that line becomes enabled and applies a set signal to its flip-flop; n-1 reset gate means, each such means including at least one reset gate, one reset gate means for each flip-flop other than the flip-flop for storing the request for service signal of highest priority, each such gate means coupled to the reset terminal of a different flip-flop; means responsive to any set flip-flop of said register for priming a reset gate for each flip-flop of said register for storing a signal of lower priority than said set flip-flop; means responsive to any set flip-flop of said register for producing a disabling signal after a first delay interval Delta t1 and applying it to all input gates to said set terminals of said flip-flops; and means responsive to said disabling signal for producing a reset signal after an additional delay interval Delta t2 and for applying that reset signal to all of said reset gate means, whereby when there is more than one flip-flop which is set, all except one of these flip-flops become reset, the flip-flop remaining set being the one storing the request for service signal of highest priority in the more than one previously set flip-flops.

Claim 6

A circuit as set forth in claim 3, further including: n output gates each connected to a different flip-flop; and means responsive to said disabling signal for producing a priming signal after an additional delay interval Delta t3 and for applying that priming signal to all of said output gates, whereby the one flip-flop which is set enables its output gate, and all of the remaining output gates, while primed, are disabled by the reset flip-flops connected to these gates.