Frequency comparator using digital circuits

Claim 2

A control device for providing an indication of the quantitative difference between a fixed and measured value, comprising a comparison counter for accumulating a count corresponding to said measured value, a plurality of presetting means, each containing a fractional proportion of said fixed value, a first of said presetting means coupled to said comparison counter for providing an indication of equality between the fractional proportion of said fixed value stored in said first of said presetting means and said corresponding proportion of said measured value reached by said comparison counter, a second of said presetting means coupled to a frequency divider and said comparison counter for providing an indication of equality between a further fractional proportion of said fixed value stored in said second of said presetting means and said corresponding proportion of said measured value reached by said comparison counter, means for providing common timing signals to said frequency divider and said comparison counter, and further means coupled to said comparison counter for providing time and polarity signals indicative of the deviation between said fixed and measured values at the moment of a timing signal.

Claim 3

A device as claimed in claim 1 wherein said means for providing time and polarity signals corresponding to the control deviation includes said presetting member controlled by the output of the comparison counter for the coarse adjustment of the desired value, and further comprising a first bistable trigger having first and second inputs connected respectively to said output of said counter and by the pulses of a time base, first and seCond gates connected by their respective inputs to the first and second outputs of said first bistable trigger and in common to the output of said presetting member, the output of said first and second gates respectively coupled to the first and second inputs of a second bistable trigger, a third bistable trigger controlled by said second output of said first trigger and supplying half the clock-pulse frequency along an output thereof, a third AND gate coupled to the output of the third bistable trigger and said first AND gate, the output of said third AND gate coupled through an inverter stage, fourth and fifth AND gates connected by their respective inputs to first and second outputs of said second bistable trigger, to the output of the inverter stage and to said second output of said first trigger, the outputs of said fourth and fifth gates providing time intervals proportional to the control deviation and coupled to the respective inputs of sixth and seventh AND gates with the output of said third trigger, the outputs of said sixth and seventh gates providing pulse numbers proportional to the control departure, a source of measured pulses, a summation stage coupled to the output of said seventh gate and said first gate and to said source of measured pulses, an anticoincidence stage connected between said comparison counter, said summation stage and the output of said sixth AND gate, and further AND gate means having one input coupled to the output of said first AND gate and a further input coupled to the output of said second presetting means, said further AND gate means having an output coupled to said comparison counter for resetting said counter in accordance with signals appearing at the output of said further AND gate means.

Claim 4

A device as claimed in claim 2 comprising a plurality of control devices, said frequency divider common to all control devices and comprising a counter controlled at the input by the pulses of a time base, an associated decoding member and a logical selection circuit, the outputs thereof being present at predetermined instants.

Claim 5

A time proportional control device for producing a time proportional control signal indicating deviation between a measured and prescribed signal, comprising a source of time base signals, a counter, means applying a measured signal to said counter, a source of counting signals, first gating means responsive to a time base signal for combining said measured signal with said counting signals, said counter thereby changing rates and counting thereafter at said combined signals rate, a coarse selection circuit coupled to said counter and having preset therein the value of a fractional proportion of said prescribed signal, said selection circuit responsive to said counter for raising said value by one, a fine selection circuit coupled by a fine selection gating means to said counter and having preset therein a further fractional proportion of said prescribed signal, said coarse selection circuit responsive to an equality of a corresponding count portion in said counter with respect to said fractional proportion of said prescribed count preset in said coarse selection circuit to produce an output signal, second gating means responsive to said output signal for blocking said first gating means and providing a counter reset signal to said fine selection gating means, said fine selecting gating means responsive to an equality of count between said counter and said further fractional proportion of said prescribed signal preset in said fine selection circuit to provide an output signal from said fine selection gating means to reset said counter, the duration between time base and reset being said time proportional control signal.

Claim 6

A time proportional control device for producing a time proportional control signal indicating deviation between a measured and prescribed signal, comprising a source of time base signals, a counter, means applying a measured signal to said counter, a source of counting signals, first gating means responsive to a time base signal for combining said measured signal with said counting signals, said counter thereby changing rates and counting thereafter at said combined signals rate, a coarse selection circuit coupled to said counter and having preset therein the value of a fractional proportion of said prescribed signal, said selection circuit responsive to said counter for raising said value by one, a fine selection circuit coupled by a fine selection gating means to said counter and having preset therein a further fractional proportion of said prescribed signal, said coarse selection circuit responsive to an equality of a corresponding count portion in said counter with respect to said fractional proportion of said prescribed count preset in said coarse selection circuit to produce an output signal, second gating means responsive to said output signal for blocking said first gating means and providing a counter reset signal to said fine selection gating means, said fine selecting gating means responsive to an equality of count between said counter and said further fractional proportion of said prescribed signal preset in said fine selection circuit to provide an output signal from said fine selection gating means to reset said counter, the duration between time base and reset being said time proportional control signal.