Bit rate synchronizer for clock and pulse code modulated signals

Claim 1

An apparatus for synchronizing the bit rate of a clock pulse signal with the bit rate of a modulated pulse signal, comprising: clock signal source means for providing the clock pulse signal; modulated signal source means for providing the modulated pulse signal; pulse generator means connected to receive the clock signal and the modulated signal for producing first and second pulses of such duration that the difference in the duration of the first and second pulses represents the difference in the bit rates of the clock signal and the modulated signal; integrator means connected to receive the first and second pulses for integrating the difference between the first and second pulses to obtain a reference signal; adjustable bias signal source means for producing a variable bias signal; and mixer means connected to receive the reference signal and the bias signal for mixing the reference signal and the bias signal to obtain a control signal, the control signal having a polarity representing the sense of the difference in the bit rates of the clock signal and the modulated signal and having a magnitude representing the degree of the difference in the bit rates of the clock signal and the modulated signal; the clock signal source means connected to receive the control signal for varying the bit rate of the clock signal in a sense responsive to the polarity of the control signal and to a degree responsive to the magnitude of the control signal so as to synchronize the bit rate of the clock signal with the bit rate of the modulated signal; whereby once the bit rates of the clock signal and the modulated signal have been initially synchronized, the bias signal may be varied so as to make the reference signal zero thereby to preserve synchronization during periods when transmission of the modulated signal is interrupted by maintaining the control signal which is provided by the bias signal.

Claim 2

An apparatus for synchronizing the bit rate of a clock pulse signal with the bit rate of a modulated pulse signal, comprising: clock signal source means for providing the clock pulse signal; modulated signal source means for providing the modulated pulse signal; pulse generator means connected to receive the clock signal and the modulated signal for producing first and second pulses of such duration that the difference in the duration of the first and second pulses represents the difference in the bit rates of the clock signal and the modulated signal; integrator means connected to receive the first and second pulses for integrating the difference between the first and second pulses to obtain a reference signal; adjustable bias signal source means for producing a variable bias signal; and mixer means connected to receive the reference signal and the bias signal for mixing the reference signal and the bias signal to obtain a control signal, the control signal having a polarity representing the sense of the difference in the bit rates of the clock signal and the modulated signal and having a magnitude representing the degree of the difference in the bit rates of the clock signal and the modulated signal; the clock signal source means connected to receive the control signal for varying the bit rate of the clock signal in a sense responsive to the polarity of the control signal and to a degree responsive to the magnitude of the control signal so as to synchronize the bit rate of the clock signal with the bit rate of the modulated signal; whereby once the bit rates of the clock signal and the modulated signal have been initially synchronized, the bias signal may be varied so as to make the reference signal zero thereby to preserve synchronization during periods when transmission of the modulated signal is interrupted by maintaining the control signal which is provided by the bias signal.

Claim 3

An apparatus for synchronizing the bit rate of a bilevel clock pulse signal with the bit rate of a bilevel modulated pulse signal, the clock signal and the modulated signal including successive voltage level transitions between an upper voltage level and a lower voltage level, the apparatus comprising: clock signal source means for providing the clock pulse signal; modulated signal source means for providing the modulated signal; pulse generator means connected to receive the clock signal and the modulated signal for producing first and second pulses, the first pulse being initiated in response to an upper-to-lower voltage level transition in the modulated signal and terminated in response to the next upper-to-lower voltage level transition in the clock signal following the upper-to-lower voltage level transItion in the modulated signal, the second pulse being initiated in response to the next upper-to-lower voltage level transition in the clock signal following an upper-to-lower voltage level transition in the modulated signal and being terminated in response to the next lower-to-upper voltage level transition in the clock signal; first and second voltage control means connected to receive the first and second pulse signals for providing first and second voltage signals of equal magnitude, of opposite polarity, and of a duration equal to the duration of the first and second pulse signals, respectively; voltage summing means connected to receive the first and second voltage signals for averaging the first and second voltage signals to obtain a reference signal; adjustable bias signal source means for producing a variable bias signal; and mixer means connected to receive the reference signal and the bias signal for mixing the reference signal with the bias signal to obtain a control signal, the control signal having a polarity representing the sense of the difference in the bit rates of the clock signal and modulated signal, and having a magnitude representing the degree of the difference in the bit rates of the clock signal and the modulated signal; the clock signal source means connected to receive the control signal for varying the bit rate of the clock signal in a sense responsive to the polarity of the control signal and to a degree responsive to the magnitude of the control signal so as to synchronize the bit rate of the clock signal with the bit rate of the modulated signal; whereby once the bit rates of the clock signal and the modulated signal have been initially synchronized, the bias signal may be varied so as to make the reference signal zero thereby to preserve synchronization during periods when transmission of the modulated signal is interrupted by maintaining the control signal which is provided by the bias signal.

Claim 4

An apparatus for synchronizing the bit rate of a bilevel clock pulse signal with the bit rate of a bilevel modulated pulse signal, the clock signal and the modulated signal including successive voltage level transitions between an upper voltage level and a lower voltage level, the apparatus comprising: clock signal source means for providing the clock pulse signal; modulated signal source means for providing the modulated signal; pulse generator means connected to receive the clock signal and the modulated signal for producing first and second pulses, the first pulse being initiated in response to an upper-to-lower voltage level transition in the modulated signal and terminated in response to the next upper-to-lower voltage level transition in the clock signal following the upper-to-lower voltage level transItion in the modulated signal, the second pulse being initiated in response to the next upper-to-lower voltage level transition in the clock signal following an upper-to-lower voltage level transition in the modulated signal and being terminated in response to the next lower-to-upper voltage level transition in the clock signal; first and second voltage control means connected to receive the first and second pulse signals for providing first and second voltage signals of equal magnitude, of opposite polarity, and of a duration equal to the duration of the first and second pulse signals, respectively; voltage summing means connected to receive the first and second voltage signals for averaging the first and second voltage signals to obtain a reference signal; adjustable bias signal source means for producing a variable bias signal; and mixer means connected to receive the reference signal and the bias signal for mixing the reference signal with the bias signal to obtain a control signal, the control signal having a polarity representing the sense of the difference in the bit rates of the clock signal and modulated signal, and having a magnitude representing the degree of the difference in the bit rates of the clock signal and the modulated signal; the clock signal source means connected to receive the control signal for varying the bit rate of the clock signal in a sense responsive to the polarity of the control signal and to a degree responsive to the magnitude of the control signal so as to synchronize the bit rate of the clock signal with the bit rate of the modulated signal; whereby once the bit rates of the clock signal and the modulated signal have been initially synchronized, the bias signal may be varied so as to make the reference signal zero thereby to preserve synchronization during periods when transmission of the modulated signal is interrupted by maintaining the control signal which is provided by the bias signal.

Claim 5

An apparatus for synchronizing the bit rate of a bilevel clock pulse signal with the bit rate of a bilevel modulated pulse signal, the clock signal and the modulated signal including successive voltage level transitions between an upper voltage level and a lower voltage level, the apparatus comprising: oscillator means for providing the dock pulse signal; modulated signal source means for providing the modulated pulse signal; pulse generator means connected to receive the clock signal and the modulated signal for producing first and second pulses, the first pulse being initiated in response to an upper-to-lower voltage level transition in the modulated signal and being terminated in response to the next upper-to-lower voltage level transition in the clock signal following the upper-to-lower voltage level transition in the modulated signal, the second pulse being initiated in response to the next upper-to-lower voltage level transition in the clock signal following an upper-to-lower voltage level transition in the modulated signal and being terminated in response to the next lower-to-upper voltage level transition in the clock signal; first and second voltage sources for providing first and second voltages of equal magnitude and of opposite polarity; first switching means connected to receive the first voltage and the first pulse for providing a first voltage signal having a duration equal to the duration of the first pulse; second switching means connected to receive the second voltage and the second pulse for providing a second voltage signal having a duration equal to the duration of the second pulse; capacitance means connected to receive the first and second voltage signals for integrating the first and second voltage signals to provide a reference signal; manually adjustable potentiometer means for providing a variable bias signal; and differential amplifier means connected to receive the reference signal and the bias signal for mixing the reference signal with the bias signal to obtain a control signal, the control signal having a polarity represEnting the sense of the difference in the bit rates of the clock signal and the modulated signal and having a magnitude representing the degree of the difference in the bit rates of the clock signal and the modulated signal; the oscillator means connected to receive the control signal for varying the bit rate of the clock signal in a sense responsive to the polarity of the control signal and to a degree responsive to the magnitude of the control signal so as to synchronize the bit rate of the clock signal with the bit rate of the modulated signal; whereby once the bit rates of the clock signal and the modulated signal have been initially synchronized, the bias signal may be varied so as to make the reference signal zero thereby to preserve synchronization during periods when transmission of the modulated signal is interrupted by maintaining the control signal which is provided by the bias signal.

Claim 6

An apparatus for synchronizing the bit rate of a bilevel clock pulse signal with the bit rate of a bilevel modulated pulse signal, the clock signal and the modulated signal including successive voltage level transitions between an upper voltage level and a lower voltage level, the apparatus comprising: oscillator means for providing the dock pulse signal; modulated signal source means for providing the modulated pulse signal; pulse generator means connected to receive the clock signal and the modulated signal for producing first and second pulses, the first pulse being initiated in response to an upper-to-lower voltage level transition in the modulated signal and being terminated in response to the next upper-to-lower voltage level transition in the clock signal following the upper-to-lower voltage level transition in the modulated signal, the second pulse being initiated in response to the next upper-to-lower voltage level transition in the clock signal following an upper-to-lower voltage level transition in the modulated signal and being terminated in response to the next lower-to-upper voltage level transition in the clock signal; first and second voltage sources for providing first and second voltages of equal magnitude and of opposite polarity; first switching means connected to receive the first voltage and the first pulse for providing a first voltage signal having a duration equal to the duration of the first pulse; second switching means connected to receive the second voltage and the second pulse for providing a second voltage signal having a duration equal to the duration of the second pulse; capacitance means connected to receive the first and second voltage signals for integrating the first and second voltage signals to provide a reference signal; manually adjustable potentiometer means for providing a variable bias signal; and differential amplifier means connected to receive the reference signal and the bias signal for mixing the reference signal with the bias signal to obtain a control signal, the control signal having a polarity represEnting the sense of the difference in the bit rates of the clock signal and the modulated signal and having a magnitude representing the degree of the difference in the bit rates of the clock signal and the modulated signal; the oscillator means connected to receive the control signal for varying the bit rate of the clock signal in a sense responsive to the polarity of the control signal and to a degree responsive to the magnitude of the control signal so as to synchronize the bit rate of the clock signal with the bit rate of the modulated signal; whereby once the bit rates of the clock signal and the modulated signal have been initially synchronized, the bias signal may be varied so as to make the reference signal zero thereby to preserve synchronization during periods when transmission of the modulated signal is interrupted by maintaining the control signal which is provided by the bias signal.