Dual input electronic timing circuit with resistor tap switching circuit

Claim 1

An electronic timing circuit energized from a direct current supply which is responsive to at least two inputs and wherein the timing function is synchronized with an AC supply voltage comprising: a. a series resistance-capacitance circuit including a timing resistance and a timing capacitor connected to be energized by the direct current supply such that said timing capacitor is charged through said timing resistance from the direct current supply; b. said timing resistance comprising a presettable resistor tap switching circuit whereby a variable timing interval in predetermined cycle increments may be selected; c. a first circuit means normally preventing the charging of said timing capacitor through said presettable resistor tap switching circuit and permitting the charging of said timing capacitor through said presettable resistor tap switching circuit in response to a first input; d. said first circuit means including a transistor which normally conducts to prevent the charging of said timing capacitor and which in response to said first input stops conducting to permit the charging of said timing capacitor; e. a unijunction transistor having two base terminals and an emitter terminal, said base terminals connected to be energized by said direct current supply to establish an interbase voltage, said unijunction transistor normally exhibiting a high impedance characteristic between a first of said base terminals and said emitter terminal, and exhibiting a low impedance characteristic between said first base terminal and said emitter terminal when said interbase voltage exceeds a predetermined voltage, and said emitter voltage is at least a predetermined fixed fraction of said interbase voltage; f. means connecting said emitter terminal to said timing capacitor such that said emitter voltage is established by the charge on said timing capacitor; g. a semiconductive device having a pair of terminals connected in series with said first base of said unijunction transistor, said semiconductive device normally exhibiting a high impedance between said pair of terminals and exhibiting a low impedance between said pair of terminals in response to receiving a second input at a third terminal, such that said interbase voltage of said unijunction transistor exceeds said predetermined minimum voltage only when said semiconductive device exhibits a low impedance between said pair of terminals, said unijunction transistor exhibiting a low impedance characteristic between said first base terminal and said emitter terminal to provide an output from the timing circuit a predetermined time after a first input permits the charging of said timing capacitor to commence, and when said semiconductive device exhibits a low impedance in response to receiving a second input at its third terminal; h. a differentiating circuit connected to receive clock pulses from said AC supply voltage and to provide very short pulses coincident with the beginning of a cycle of the AC supply as said second input to said third terminal of said semiconductive device whereby said unijunction transistor will commence to exhibit a low impedance between said first terminal and said emitter terminal to provide an output only at the beginning of a cycle of the AC supply; and i. a transistor flip-flop output circuit, the transistors of said flip-flop output circuit normally being maintained in the reset condition and being switched to the ''''ON'''' condition when said unijunction transistor exhibits a low impedance characteristic.