US3575591A
Expired / Lapsed
US
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Addition circuit for the digital codes generated in accordance with a nonlinear compression law
Assignee: International Standard Electric Corp
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Filing: 1968-09-27
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Granted: 1971-04-20
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Expires: 1988-09-27
Abstract
Abstract There is disclosed an arrangement including a translator to derive two linear code signals from two compressed code signals and compressing the resultant sum of the two linear code signals in the translator after addition in an adder circuit. The translator comprises a shift register operating in two directions and a counter.
Inventors
- 👤 Andre Edouard Joseph Chatelon
- 👤 Calude Paul Henri Lerouge
- 👤 Jean Perrault
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:30
CPC Classifications
H; H04; H04M; H04M3/00; H04M3/42; H04M3/56; H04M3/561
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
97 words
An addition circuit for two digital code signals each having n digits, where n is an integer greater than one, and generated by coding according to an approximate nonlinear compression law comprising: input means for said two code signals; first means coupled to said input means to translate said two code signals into two linear code signals; second means coupled to said first means to add said two linear code signals together; and third means coupled to said second means to compress the sum of said two linear code signals according to said approximate nonlinear compression law.
Claim 2
Dependent Claim
97 words
An addition circuit for two digital code signals each having n digits, where n is an integer greater than one, and generated by coding according to an approximate nonlinear compression law comprising: input means for said two code signals; first means coupled to said input means to translate said two code signals into two linear code signals; second means coupled to said first means to add said two linear code signals together; and third means coupled to said second means to compress the sum of said two linear code signals according to said approximate nonlinear compression law.
Claim 3
Dependent Claim
70 words
A circuit according to claim 1, wherein said input means includes logic circuit means responsive to said two code signals, first register means coupled to said logic circuit means for storing (n- 1) digits of one of said two code signals or its complement, and second register means coupled to said logic circuit means for storing (n- 1) digits of the other of said two code signals or its complement.
Claim 4
Dependent Claim
28 words
A circuit according to claim 1, wherein said first means is further coupled to the output of said second means and performs the functions of said third means.
Claim 5
Dependent Claim
31 words
A circuit according to claim 3, wherein said first means includes shift register means coupled to said input means operating in two directions, and counter means coupled to said input means.
Claim 6
Dependent Claim
122 words
A circuit according to claim 1, wherein said input means includes logic circuit means responsive to said two code signals, first register means coupled to said logic circuit means for storing (n31 1) digits of one of said two code signals or its complement, and second register means coupled to said logic circuit means for storing (n- 1) digits of the other of said two code signals or its complement; and said first means is further coupled to the output of said second means and performs the function of said third means; said first means including shift register means coupled to said first and second register means operating in two directions, and counter means coupled to said first and second register means.
Claim 7
Dependent Claim
18 words
A circuit according to claim 1, wherein said approximate nonlinear compression law is an approximate logarithmic compression law.
Claim 8
Dependent Claim
70 words
A circuit according to claim 6, wherein said input means includes logic circuit means responsive to said two code signals, first register means coupled to said logic circuit means for storing (n- 1) digits of one of said two code signals or its complement, and second register means coupled to said logic circuit means for storing (n- 1) digits of the other of said two code signals or its complement.
Claim 9
Dependent Claim
28 words
A circuit according to claim 6, wherein said first means is further coupled to the output of said second means and performs the functions of said third means.
Claim 10
Dependent Claim
31 words
A circuit according to claim 8, wherein said first means includes shift register means coupled to said input means operating in two directions, and counter means coupled to said input means.
Claim 11
Dependent Claim
122 words
A circuit according to claim 6, wherein said input means includes logic circuit means responsive to said two code signals, first register means coupled to said logic circuit means for storing (n- 1) digits of one of said two code signals or its complement, and second register means coupled to said logic circuit means for storing (n- 1) digits of the other of said two code signals or its complement; and said first means is further coupled to the output of said second means and performs the function of said third means; said first means including shift register means coupled to said first and second register means operating in two directions, and counter means coupled to said first and second register means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-19 | 1974-10-19 | 1975-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-19 | 1978-10-19 | 1979-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-19 | 1982-10-19 | 1983-04-20 | $7700.00 | Window Closed / Lapsed |