US3573572A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controlled rectifier having high rate-of-rise-of-current capability and low firing gate current
Assignee: Infineon Technologies Americas Corp
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Filing: 1968-09-23
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Granted: 1971-04-06
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Expires: 1988-09-23
Abstract
Abstract A semiconductor controlled rectifier having an auxiliary cathode region and a main cathode region with a main control gate lead disposed adjacent to the auxiliary cathode region. The controlled rectifier including the auxiliary cathode region can be fired by a relatively low gate current. The output current of the auxiliary cathode region is connected to auxiliary gates disposed in proximity to the main cathode and supplies necessary current for turning on the main portion of the controlled rectifier.
Inventors
- 👤 David Cooper
- 👤 Harold Weinstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:25
CPC Classifications
H; H10; H10D; H10D18/00; E; E04; E04D; E04D3/00; E04D3/36; H10D1/00; H10D1/40; H10D48/00; H10D48/30; H10D48/38; H10D62/00; H10D62/10; H10D62/13; H10D64/00; H10D64/20; H10D64/23; H10D64/27; H10D99/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
281 words
A controllably conductive semiconductor device having a high rate-of-rise-of-current capability and which can be fired with a relatively low gate current, comprising: a wafer of monocrystalline semiconductor material having first and second parallel surfaces; first, second and third spaced P-N junctions sequentially disposed therein; at least a portion of said third P-N junction terminating along said first surface of said wafer and dividing said first surface into a first surface region extending atop said third P-N junction and into a second surface region; a first main electrode connected to said first surface region of said first surface; a second main electrode connected to said second surface of said wafer; a fourth P-N junction disposed beneath said second surface region of said first surface and above said second P-N junction and being laterally displaced from said third P-N junction solely at one side thereof; an auxiliary electrode connected to said second surface region atop said fourth junction; said auxiliary electrode having a surface area smaller than the surface area of said first main electrode; a main gate electrode connected to said second surface region adjacent said auxiliary electrode; and an auxiliary gate electrode connected to said auxiliary electrode and to said second surface region of said wafer and adjacent to said first main electrode; said auxiliary electrode and said auxiliary gate electrode comprising a common conductive electrode extending across said fourth P-N junction; said auxiliary electrode being disposed between said main gate electrode and said first main electrode; the confronting edges of said first main electrode and said common conductive electrode being substantially coextensive; said common conductive electrode and said first main electrode consisting of spaced segments of a common metallic disc.
Claim 2
Dependent Claim
281 words
A controllably conductive semiconductor device having a high rate-of-rise-of-current capability and which can be fired with a relatively low gate current, comprising: a wafer of monocrystalline semiconductor material having first and second parallel surfaces; first, second and third spaced P-N junctions sequentially disposed therein; at least a portion of said third P-N junction terminating along said first surface of said wafer and dividing said first surface into a first surface region extending atop said third P-N junction and into a second surface region; a first main electrode connected to said first surface region of said first surface; a second main electrode connected to said second surface of said wafer; a fourth P-N junction disposed beneath said second surface region of said first surface and above said second P-N junction and being laterally displaced from said third P-N junction solely at one side thereof; an auxiliary electrode connected to said second surface region atop said fourth junction; said auxiliary electrode having a surface area smaller than the surface area of said first main electrode; a main gate electrode connected to said second surface region adjacent said auxiliary electrode; and an auxiliary gate electrode connected to said auxiliary electrode and to said second surface region of said wafer and adjacent to said first main electrode; said auxiliary electrode and said auxiliary gate electrode comprising a common conductive electrode extending across said fourth P-N junction; said auxiliary electrode being disposed between said main gate electrode and said first main electrode; the confronting edges of said first main electrode and said common conductive electrode being substantially coextensive; said common conductive electrode and said first main electrode consisting of spaced segments of a common metallic disc.
Claim 3
Dependent Claim
27 words
The device of claim 1 wherein said confronting edges of said common conductive electrode and of said first main electrode have respective extending fingers which are interleaved.
Claim 4
Dependent Claim
30 words
The device of claim 1 wherein said first main electrode extends from said first surface region and across said third junction and to a portion of said second surface region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |