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US3573506A Expired / Lapsed US ⏱️ 0.0 years remaining

Temperature stabilized monstable multivibrator

Assignee: Individual
•
Filing: 1968-05-08
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Granted: 1971-04-06
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Expires: 1988-05-08
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Abstract

Abstract A modification to a conventional monostable multivibrator circuit is disclosed for minimizing variations in the width of output pulses produced by the circuit, in particular, pulse width variations resulting from changes in parameters of the transistors resulting from temperature variations. Stabilization is achieved by utilizing an additional transistor as a leg of a voltage divider for supplying bias voltage to the transistors of the multivibrator. When the additional transistor has a temperature response similar to that of the multivibrator transistor, a circuit can be constructed that compensates for changes in parameters of the multivibrator transistors by changing their bias voltage. Two embodiments of the instant invention are disclosed. One utilizes a third transistor that is identical in type to the transistor of the multivibrator while the other uses a transistor of complementary symmetry.

Inventors

  • 👤 Francis E Morris

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 13:34
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/284

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 252 words
In a solid-state voltage-variable monostable multivibrator circuit of the type comprising: first and second transistor stages responsive to a bias voltage applied to said first stage for normally maintaining said first stage in a ''''OFF'''' condition and said second stage in an ''''ON'''' condition; said first stage being responsive to input trigger pulses of a predetermined polarity such that said first stage is caused to turn ''''ON'''' by receipt of one of such pulses; means for coupling said first stage to said second stage so that turning said first stage ''''ON'''' causes said second stage to turn ''''OFF'''' for a predetermined time period; said time period being a determinable function of the bias voltage applied to said first stage transistor; the improvement comprising means for stabilizing said time period and comprising; a voltage divider comprising a constant resistance and the variable resistance developed between the emitter and collector of a third transistor serially connected with a source of voltage, said third transistor being arranged to accept pulses as an input to its base, and the series connection between said constant resistance and said third transistor being connected to provide the base of said first stage transistor with biasing voltage, and with input trigger pulses; and said third transistor being selected to vary its resistance in response to temperature changes and in a manner related to the change in parameters of said first stage transistor with temperature, whereby to provide a biasing voltage as a function of temperature and stabilize said time period.
Claim 2
Dependent Claim 252 words
In a solid-state voltage-variable monostable multivibrator circuit of the type comprising: first and second transistor stages responsive to a bias voltage applied to said first stage for normally maintaining said first stage in a ''''OFF'''' condition and said second stage in an ''''ON'''' condition; said first stage being responsive to input trigger pulses of a predetermined polarity such that said first stage is caused to turn ''''ON'''' by receipt of one of such pulses; means for coupling said first stage to said second stage so that turning said first stage ''''ON'''' causes said second stage to turn ''''OFF'''' for a predetermined time period; said time period being a determinable function of the bias voltage applied to said first stage transistor; the improvement comprising means for stabilizing said time period and comprising; a voltage divider comprising a constant resistance and the variable resistance developed between the emitter and collector of a third transistor serially connected with a source of voltage, said third transistor being arranged to accept pulses as an input to its base, and the series connection between said constant resistance and said third transistor being connected to provide the base of said first stage transistor with biasing voltage, and with input trigger pulses; and said third transistor being selected to vary its resistance in response to temperature changes and in a manner related to the change in parameters of said first stage transistor with temperature, whereby to provide a biasing voltage as a function of temperature and stabilize said time period.
Claim 3
Dependent Claim 18 words
The circuit of claim 1 wherein said third transistor is of complementary symmetry to said first transistor stage.
Claim 4
Dependent Claim 73 words
The circuit of claim 2 wherein said first stage includes an NPN transistor having base, emitter and collector elements and said third stage includes a PNP transistor having base, emitter and collector elements, and said base of said NPN transistor being connected to said emitter of said PNP transistor. 4 The circuit of claim 1 wherein said third transistor has the same characteristics and is of the same type as said first transistor.
Claim 5
Dependent Claim 36 words
The circuit of claim 4 wherein said first and third transistors are of the NPN type and each includes base, emitter and collector elements; and said first transistor''s base being connected to said third transistor''s collector.

References Cited (Backward Citations)

US2975300A Cited
US3214602A Cited
US2976432A Cited
US3264579A Cited
US3239778A Cited
US3356863A Cited
US3388344A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-04-05 1974-10-05 1975-04-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-04-05 1978-10-05 1979-04-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-04-05 1982-10-05 1983-04-06 $7700.00 Window Closed / Lapsed

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