High speed current-mode logic gate

Claim 2

A current-mode logic gate comprising: first and second transistors each having a base, a collector and an emitter, a signal-input terminal, said input terminal being connected to said base of said first transistor; first, second and third reference potentials; first, second and third resistors; a common-base amplifier, said common-base amplifier being connected between said collector of said first transistor and a first end of said first resistor, a second end of said first resistor being connected to said first potential, said second resistor being connected between said emitter of said first transistor and said second potential, said base of said second transistor being connected to said third potential, said emitter of said second transistor being connected to said emitter of said first transistor, said third resistor being connected between said collector of said second transistor and said first potential; and first and second output leads, said first output lead being connected to said common-base amplifier, said second output lead being connected to said collector of said second transistor.

Claim 3

A current-mode logic gate as defined in claim 1 including a third transistor having a base, a collector and an emitter; and a second signal-input terminal, said second input terminal being connected to said base of said third transistor, said emitter of said third transistor being connected to said emitter of said first transistor, said collector of said third transistor being connected to said collector of said first transistor.

Claim 4

A current-mode logic gate as defined in claim 1 including third and fourth transistors each having a base, a collector and an emitter; fourth and fifth resistors, said base of said third transistor being connected to said first output lead, said fourth resistor being connected between said emitter of said third transistor and said second potential, said fifth resistor being connected between said emitter of said fourth transistor and said second potential, said collectors of said third and said fourth transistors each being connected to said first potential, said base of said fourth transistor being connected to said second output lead; and first and second output terminals, said first output terminal being connected to said emitter of said third transistor, said second output terminal being connected to said emitter of said fourth transistor.

Claim 5

A current-mode logic gate as defined in claim 1 including third, fourth and fifth transistors each having a base, a collector and an emitter; a second signal-input terminal; and fourth and fifth resistors, said second input terminal being connected to said base of said fifth transistor, said collector of said fifth transistor being connected to said collector of said first transistor, said emitter of said fifth transistor being connected to said emitter of said first transistor, said base of said third transistor being connected to said first output lead, said base of said fourth transistor being connected to said second output lead, said fourth resistor being connected between said emitter of said third transistor and said second potential, said fifth resistor beinG connected between said emitter of said fourth transistor and said second potential, said collectors of said third and said fourth transistors being connected to said first potential; and first and second output terminals, said first output terminal being connected to said emitter of said third transistor, said second output terminal being connected to said emitter of said fourth transistor.

Claim 6

A current-mode logic gate comprising: first, second and third transistors each having a base, a collector and an emitter; a signal-input terminal, said input terminal being connected to said base of said first transistor; first, second, third and fourth reference potentials; first, second and third resistors, said collector of said first transistor being connected to said emitter of said third transistor, said first resistor being connected between said collector of said third transistor and said first potential, said base of said second transistor being connected to said third potential, said base of said third transitor being connected to said fourth potential, said second resistor being connected between said emitter of said first transitor and said second potential, said emitter of said second transistor being connected to said emitter of said first transistor, said third resistor being connected between said collector of said second transistor and said first potential; and first and second output leads, said first output lead being connected to said collector of said third transistor, said second output lead being connected to said collector of said second transistor.

Claim 7

A current-mode logic gate comprising: first, second and third transistors each having a base, a collector and an emitter; a signal-input terminal, said input terminal being connected to said base of said first transistor; first, second, third and fourth reference potentials; first, second and third resistors, said collector of said first transistor being connected to said emitter of said third transistor, said first resistor being connected between said collector of said third transistor and said first potential, said base of said second transistor being connected to said third potential, said base of said third transitor being connected to said fourth potential, said second resistor being connected between said emitter of said first transitor and said second potential, said emitter of said second transistor being connected to said emitter of said first transistor, said third resistor being connected between said collector of said second transistor and said first potential; and first and second output leads, said first output lead being connected to said collector of said third transistor, said second output lead being connected to said collector of said second transistor.

Claim 8

A current-mode logic gate as defined in claim 5 including a fourth transistor having a base, a collector and an emitter; and a second signal-input terminal, said second input terminal being connected to said base of said fourth transistor, said collector of said fourth transistor being connected to said collector of said first transistor, said emitter of said fourth transistor being connected to said emitter of said first transistor.

Claim 9

A current-mode logic gate comprising: first, second, third, fourth and fifth transistors each having a base, a collector and an emitter; a signal-input terminal, said signal-input terminal being connected to said base of said first transistor; first, second, third and fourth reference potentials, said collector of said first transistor being connected to said emitter of said third transistor, said base of said second transistor being connected to said third potential, said base of said third transistor being connected to said fourth potential; first, second, third, fourth and fifth resistors, said first resistor being connected between said collector of said third transistor and said first potential, said second resistor being connected between said second potential and said emitters of said first and said second transistors, said third resistor being connected between said first potential and said collector of said second transistor, said base of said fourth transistor being connected to said collector of said second transistor, said base of said fifth transistor being connected to said collector of said third transistor, said collectors of said fourth and said fifth transistors being connected to said first potential, said fourth resistor being connected between said second potential and said emitter of said fourth transistor, said fifth resistor being connected between said second potential and said emitter of said fifth transistor; and first and second output terminals, said first output terminal being connected to said emitter of said fourth transistor, said second output terminal being connected to said emitter of said fifth transistor.

Claim 10

A current-mode logic gate comprising: first, second, third, fourth and fifth transistors each having a base, a collector and an emitter; a signal-input terminal, said signal-input terminal being connected to said base of said first transistor; first, second, third and fourth reference potentials, said collector of said first transistor being connected to said emitter of said third transistor, said base of said second transistor being connected to said third potential, said base of said third transistor being connected to said fourth potential; first, second, third, fourth and fifth resistors, said first resistor being connected between said collector of said third transistor and said first potential, said second resistor being connected between said second potential and said emitters of said first and said second transistors, said third resistor being connected between said first potential and said collector of said second transistor, said base of said fourth transistor being connected to said collector of said second transistor, said base of said fifth transistor being connected to said collector of said third transistor, said collectors of said fourth and said fifth transistors being connected to said first potential, said fourth resistor being connected between said second potential and said emitter of said fourth transistor, said fifth resistor being connected between said second potential and said emitter of said fifth transistor; and first and second output terminals, said first output terminal being connected to said emitter of said fourth transistor, said second output terminal being connected to said emitter of said fifth transistor.

Claim 11

A current-mode logic gate as defined in claim 7 including a sixth transistor having a base, a collector and an emitter; and a second signal-input terminal, said second input terminal being connected to said base of said sixth transistor, said collector of said sixth transistor being connected to said collector of said fIrst transistor, said emitter of said sixth transistor being connected to said emitter of said first transistor.

Claim 12

A current-mode logic gate comprising: first, second, third, fourth and fifth transistors each having a base, a collector and an emitter; a signal-input terminal, said signal-input terminal being connected to said base of said first transistor; first, second, third, fourth and fifth reference potentials, said collector of said first transistor being connected to said emitter of said third transistor, said base of said second transistor being connected to said third potential, said base of said third transistor being connected to said fourth potential; first, second, third, fourth and fifth resistors, said first resistor being connected between said collector of said third transistor and said first potential, said second resistor being connected between said second potential and said emitters of said first and said second transistors, said third resistor being connected between said first potential and said collector of said second transistor, said base of said fourth transistor being connected to said collector of said second transistor, said base of said fifth transistor being connected to said collector of third said third transistor, said collectors of said fourth and said fifth transistors being connected to said first potential, said fourth resistor being connected between said fifth potential and said emitter of said fourth transistor, said fifth resistor being connected between said fifth potential and said emitter of said fifth transistor; and first and second output terminals, said first output terminal being connected to said emitter of said fourth transistor, said second output terminal being connected to said emitter of said fifth transistor.

Claim 13

A current-mode logic gate comprising: first, second, third, fourth and fifth transistors each having a base, a collector and an emitter; a signal-input terminal, said signal-input terminal being connected to said base of said first transistor; first, second, third, fourth and fifth reference potentials, said collector of said first transistor being connected to said emitter of said third transistor, said base of said second transistor being connected to said third potential, said base of said third transistor being connected to said fourth potential; first, second, third, fourth and fifth resistors, said first resistor being connected between said collector of said third transistor and said first potential, said second resistor being connected between said second potential and said emitters of said first and said second transistors, said third resistor being connected between said first potential and said collector of said second transistor, said base of said fourth transistor being connected to said collector of said second transistor, said base of said fifth transistor being connected to said collector of third said third transistor, said collectors of said fourth and said fifth transistors being connected to said first potential, said fourth resistor being connected between said fifth potential and said emitter of said fourth transistor, said fifth resistor being connected between said fifth potential and said emitter of said fifth transistor; and first and second output terminals, said first output terminal being connected to said emitter of said fourth transistor, said second output terminal being connected to said emitter of said fifth transistor.

Claim 14

A high fan-out logic circuit formed on a block of semiconductor material comprising: a current-mode logic gate including a plurality of common-emitter amplifiers, said gate having a plurality of signal-input terminals and first and second output leads; first and second reference potentials; a common-base transistor amplifier having an input lead and an output lead, said input lead of said common-base amplifier being connected to said first output lead of said gate; first and second output transistors each having a base, a collector and an emitter, said base of said first output transistor being connected to said output lead of said common-base amplifier, said base of said second output transistor being connected to said second output lead of said gate, said collectors of said first and said second output transistors each being connected to said first potential; first and second output terminals; first and second resistors; means for connecting said second potential to a first end of said first and said second resistors; means for connecting said emitter of said first output transistor to a second end of said first resistor; and means for connecting said emitter of said second output transistor to a second end of said second resistor, said first output terminal being connected to said emitter of said first output transistor, said second output terminal being connected to said emitter of said second output transistor.

Claim 15

A high fan-out logic circuit formed on a block of semiconductor material comprising: a current-mode logic gate including a plurality of common-emitter amplifiers, said gate having a plurality of signal-input terminals and first and second output leads; first and second reference potentials; a common-base transistor amplifier having an input lead and an output lead, said input lead of said common-base amplifier being connected to said first output lead of said gate; first and second output transistors each having a base, a collector and an emitter, said base of said first output transistor being connected to said output lead of said common-base amplifier, said base of said second output transistor being connected to said second output lead of said gate, said collectors of said first and said second output transistors each being connected to said first potential; first and second output terminals; first and second resistors; means for connecting said second potential to a first end of said first and said second resistors; means for connecting said emitter of said first output transistor to a second end of said first resistor; and means for connecting said emitter of said second output transistor to a second end of said second resistor, said first output terminal being connected to said emitter of said first output transistor, said second output terminal being connected to said emitter of said second output transistor.

Claim 16

A high fan-out logic circuit as defined in claim 10 wherein: said resistors are formed in said block of semiconductor material adjacent to said output terminals.