Pulse circuit

Claim 2

A pulse circuit comprising a voltage source, a pair of controlled switches each having a control electrode, said switches being serially connected in like polarity across said voltage source, a signal source, and means connected between said signal source and said control electrodes responsive to the initial portion of a signal from said source for concurrently applying a switch-disabling pulse to one control electrode and a switch-enabling pulse to the other control electrode, and means responsive to the terminating portion of said signal for concurrently applying a switch disabling pulse to said other control electrode and for applying a switch enabling pulse to said one control electrode.

Claim 3

A pulse circuit according to claim 1 wherein each of said means for concurrently applying said switch-disabling pulse and said switch-enabling pulse comprises means for immediately applying said switch-disabling pulse to one of said control electrodes and means for applying said switch-enabling pulse comprises pulse-delaying means connected between said signal source and the other of said control electrodes.

Claim 4

A pulse circuit according to claim 1 wherein said means for immediately applying said switch-disabling pulse comprises first means for transmitting a pulse of one polarity to said corresponding control electrode and said pulse delaying means comprises second means for applying a pulse of the opposite polarity to said corresponding control electrode.

Claim 5

A pulse circuit according to claim 3 wherein said means for transmitting a pulse of one polarity comprises unidirectional conducting means connected between said signal source and said control electrode and said pulse delaying means comprises a delay network connected between said signal source and said control electrode.

Claim 6

A pulse circuit according to claim 4 wherein said delay network comprises a resistor-capacitor integrating network.

Claim 7

A circuit for generating a pair of sequential, opposite polarity pulses comprising a voltage source; first and second controlled switches each having a control gate, an anode, and a cathode; said first switch anode being connected to said voltage source; said first switch cathode being connected to said second switch anode; said second switch cathode being connected to a reference potential; a source of pulses; means responsive to each positive pulse transition for immediately applying a negative signal to said first switch control gate; means responsive to each positive pulse transition for applying a delayed positive signal to said second switch control gate; means responsive to each negative pulse transition for applying a delayed positive signal to said first switch control gate; and means responsive to each negative pulse transition for immediately applying a negative signal to said second switch control gate whereby said first and second controlled switches are alternately enabled.

Claim 8

A circuit for generating a pair of sequential, opposite polarity pulses comprising a voltage source; first and second controlled switches each having a control gate, an anode, and a cathode; said first switch anode being connected to said voltage source; said first switch cathode being connected to said second switch anode; said second switch cathode being connected to a reference potential; a source of pulses; means responsive to each positive pulse transition for immediately applying a negative signal to said first switch control gate; means responsive to each positive pulse transition for applying a delayed positive signal to said second switch control gate; means responsive to each negative pulse transition for applying a delayed positive signal to said first switch control gate; and means responsive to each negative pulse transition for immediately applying a negative signal to said second switch control gate whereby said first and second controlled switches are alternately enabled.

Claim 9

A pulse circuit according to claim 6 further comprising capacitor means connected to the junction of said first switch cathode and said second switch anode, said capacitor means being charged in response to the turn-on of said first switch and being discharged in response to the turn-on of said second switch.

Claim 10

A pulse circuit according to claim 6 further comprising means including resonant circuit means connected to the junction of said first switch cathode and said second switch anode for turning off each of said alternately enabled switches after a time period determined by said resonant circuit means.

Claim 11

A circuit according to claim 6 wherein transformer means are connected to said pulse source, each of said positive signal-applying means comprises a delay network connected between said transformer means and the associated switch control gate, and each of said negative signal-applying means comprises diode means connected between said transformer means and the associated switch control gate.

Claim 12

A circuit according to claim 9 wherein each of said delay networks comprises a resistor connected between said transformer means and the associated switch control gate and a capacitor connected between the control gate and the cathode of the associated switch.

Claim 13

A circuit according to claim 10 wherein each of said delayed positive signal-applying means is operative in response to each pulse transition to terminate said delayed positive signal prior to the termination of the concurrently applied negative signal.

Claim 14

A pulse circuit for generating successive high current pulses of opposite polarity in response to a control signal comprising a voltage source, a pair of control switches serially connected in like polarity across said voltage source, each said switch having a control gate, a signal source, means connected between said signal source and each of said control gates and responsive to the leading edge of a control signal from said source for immediately applying a switch-disabling pulse to the control gate of one of said switches and for concurrently applying a delayed enabling pulse to the control gate of the other of said switches, and means responsive to the trailing edge of said control signal from said source for immediately applying a switch-disabling pulse to said control gate of said other of said switches and for concurrently applying a delayed enabling pulse to said conTrol gate of said one of said switches.

Claim 15

A pulse circuit for generating successive high current pulses of opposite polarity in response to a control signal comprising a voltage source, a pair of control switches serially connected in like polarity across said voltage source, each said switch having a control gate, a signal source, means connected between said signal source and each of said control gates and responsive to the leading edge of a control signal from said source for immediately applying a switch-disabling pulse to the control gate of one of said switches and for concurrently applying a delayed enabling pulse to the control gate of the other of said switches, and means responsive to the trailing edge of said control signal from said source for immediately applying a switch-disabling pulse to said control gate of said other of said switches and for concurrently applying a delayed enabling pulse to said conTrol gate of said one of said switches.