US3571731A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed synchronous sampler control timer
Assignee: Individual
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Filing: 1969-02-25
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Granted: 1971-03-23
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Expires: 1989-02-25
Abstract
Abstract A synchronous timer that counts input pulses and operates a connected device when a preselected count is reached. The timer contains voltage control circuitry, a binary logic circuit, a coincident gate and switch for preselecting the number of pulses, a multivibrator connected to the coincident gate, a reset circuit for automatically returning the count to zero after the preselected count is reached and a relay circuit connected to the coincident gate to operate the connected device.
Inventors
- 👤 Richard E Rabe
- 👤 Ronald J Covello
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 21:35
CPC Classifications
G; G04; G04F; G04F10/00; G04F10/04; H; H03; H03K; H03K23/00; H03K23/64; H03K23/66
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
112 words
A synchronous timer comprising: a source of alternating current; a first voltage-reducing means and rectifying means connected in series to said source; a second voltage-reducing means and rectifying means connected in series to said source; counting means adapted to count signal pulses connected to the first voltage-reducing means; a first relay connected to the counting means and controlled thereby; a mode control switch; a second relay operatively connected between the first relay, the second voltage-reducing means and the mode control switch and output means controlled by said first and second relays whereby a device associated with said output means may be activated or deactivated as a timed function of the input signal.
Claim 2
Dependent Claim
112 words
A synchronous timer comprising: a source of alternating current; a first voltage-reducing means and rectifying means connected in series to said source; a second voltage-reducing means and rectifying means connected in series to said source; counting means adapted to count signal pulses connected to the first voltage-reducing means; a first relay connected to the counting means and controlled thereby; a mode control switch; a second relay operatively connected between the first relay, the second voltage-reducing means and the mode control switch and output means controlled by said first and second relays whereby a device associated with said output means may be activated or deactivated as a timed function of the input signal.
Claim 3
Dependent Claim
97 words
A synchronous timer as claimed in claim 1 wherein the counting means includes: signal-conditioning means; a binary logic circuit connected to the conditioning means; a selector switch associated with the binary logic circuit for selecting a desired count; a coincident gate; switching means connected to the logic circuit and the coincident gate whereby the counting means will produce an output upon the reaching of a preselected input signal count; a multivibrator connected to the coincident gate, and means connected between the multivibrator and logic circuit for automatically resetting the counting means after the said signal is produced.
References Cited (Backward Citations)
US3327224A
Cited
US3406295A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-22 | 1974-09-21 | 1975-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-22 | 1978-09-21 | 1979-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-22 | 1982-09-21 | 1983-03-23 | $7700.00 | Window Closed / Lapsed |