US3571692A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Step width regulated dc/dc converter
Assignee: United States Department of the Navy
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Filing: 1969-07-01
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Granted: 1971-03-23
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Expires: 1989-07-01
Abstract
Abstract A feedback regulated DC/DC converter is disclosed. More particularly, an unregulated master oscillator feeds square waves into one core of a dual-core transformer, and a slave oscillator (whose output amplitude is a predetermined fraction of the master oscillator''s output amplitude) also feeds square waves into the other core of the transformer. A sample of the transformer output after it has been rectified and filtered is compared against a reference value and the difference between the output value and the reference value produces an error current which is fed into a delay circuit. The delay circuit will then synchronously adjust the output phase of the slave oscillator. Thus, the average voltage appearing across the secondary of the dual-core transformer is varied by adjusting the relative phase between the master and the slave oscillator. Since the slave oscillator operates at only a small percent of the master oscillator''s output, step-width modulation, rather than the standard pulse width modulation, results.
Inventors
- 👤 Carl F Andren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:22
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/338; H02M3/3385; H02M3/3387; H02M3/3388
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
230 words
A DC/DC step width modulated voltage regulator comprising: a source of first periodically varying signals; a source of second periodically varying signals; means for combining said first periodically varying signals and said second periodically varying signal to produce a resultant periodically varying signal; converting means for rectifying and filtering said resultant periodically varying signal to produce a DC voltage level output; a source of reference voltage; means to compare said reference voltage with said DC output voltage to produce an error signal; and means responsive to said error signal for adjusting the phase relationship between said first and said second periodically varying signals, said phase adjusting means being a delay circuit comprising: first and second delay reactors respectively connected to the outputs of said error signal producing means and said source of first periodically varying signals, and a level sensing means connected to the output of each of first and second delay reactors, said level sensing means sensing the change from magnetizing current to saturated current in each of said first and second delay reactors, means connected to the output of said level sensing means for short circuiting said second source of periodically varying signals, whereby the output of said delay circuit is a trigger signal to said second source of periodically varying signals effective to control the phase relationship between said sources of first and second periodically varying signals.
Claim 2
Dependent Claim
230 words
A DC/DC step width modulated voltage regulator comprising: a source of first periodically varying signals; a source of second periodically varying signals; means for combining said first periodically varying signals and said second periodically varying signal to produce a resultant periodically varying signal; converting means for rectifying and filtering said resultant periodically varying signal to produce a DC voltage level output; a source of reference voltage; means to compare said reference voltage with said DC output voltage to produce an error signal; and means responsive to said error signal for adjusting the phase relationship between said first and said second periodically varying signals, said phase adjusting means being a delay circuit comprising: first and second delay reactors respectively connected to the outputs of said error signal producing means and said source of first periodically varying signals, and a level sensing means connected to the output of each of first and second delay reactors, said level sensing means sensing the change from magnetizing current to saturated current in each of said first and second delay reactors, means connected to the output of said level sensing means for short circuiting said second source of periodically varying signals, whereby the output of said delay circuit is a trigger signal to said second source of periodically varying signals effective to control the phase relationship between said sources of first and second periodically varying signals.
Claim 3
Dependent Claim
18 words
The regulator as claimed in claim 1 wherein said short-circuiting means is a pair of short circuit transistors.
Claim 4
Dependent Claim
39 words
The regulator as recited in claim 1 wherein said level sensing means comprises: first and second resistors serially connected to the outputs of said first and second delay reactors; and a pair of tunnel diodes connected between said resistors.
Claim 5
Dependent Claim
28 words
The regulator as claimed in claim 1 wherein said error signal producing means generates a pair of error signals effective to reset said first and second delay reactors.
Claim 6
Dependent Claim
34 words
The regulator as claimed in claim 1 wherein said source of said first periodically varying signals is a master oscillator and wherein said source of said second periodically varying signals is a slave oscillator.
Claim 7
Dependent Claim
30 words
The regulator as recited in claim 5 wherein said slave oscillator generates an output signal whose amplitude is a predetermined fraction of the output signal amplitude of said master oscillator.
Claim 8
Dependent Claim
66 words
The regulator as recited in claim 1 wherein said means for combining said first and secOnd periodically varying signals is a dual-core transformer comprising: first and second primary windings, each winding being wound about separate and distinct core members and connected respectively to the outputs of said master and slave oscillators; and a common secondary winding wound about both of said first and second core members.
Claim 9
Dependent Claim
57 words
The regulator as claimed in claim 7 wherein the ratio of the number of turns in the primary windings for said slave core to the number of turns in the primary winding for said master core is equal to the reciprocal of the fractional relationship between the respective output signal amplitudes from said slave and master oscillators.
Claim 10
Dependent Claim
98 words
The regulator as claimed in claim 7 wherein said secondary winding of said dual-core transformer is connected to a plurality of output taps and wherein said converting means comprises: rectifying means serially connected to each of said secondary winding output taps; inductor means having one terminal serially connected to the output of said rectifying means; capacitance means connected between the other terminal of said inductor means and ground; and means connected in parallel with said capacitance means to suppress the buildup of excessive voltage across said capacitance means, said voltage suppression means comprising serially connected resistor and diode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-22 | 1974-09-21 | 1975-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-22 | 1978-09-21 | 1979-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-22 | 1982-09-21 | 1983-03-23 | $7700.00 | Window Closed / Lapsed |