US3569956A
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Minimal logic block encoder
Assignee: National Aeronautics and Space Administration
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Filing: 1968-10-30
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Granted: 1971-03-09
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Expires: 1988-10-30
Abstract
Abstract An encoder incorporating a minimum number of logic circuits to convert 64 6-bit data words into 64 32-bit code words, forming a 32, 6 biorthogonal code. Each code bit, generated during a multiclock-period-code-bit-period, is logically combined, at the end of the code bit period, with a code bit of a comma free vector code to produce a code bit of a code word in a 32, 6 comma free biorthogonal code. The encoder implements an algorith in accordance to which each of the six data word bits is incorporated in a modulo-2 summation, as a function of the codebit number and number of logic ones in the code-bit number in binary form.
Inventors
- 👤 James O Duffy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:52
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M5/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
173 words
An encoder of the type for converting an m-bit data word into a corresponding n-bit code word herein n 2 (m 1), 1), the encoder 2 clock means for defining m clock periods during each of a sequence of n code bit periods; first means for storing said m-bit data word and for cycling said data word therethrough during the m clock periods of each code bit period; second means for storing, during each code bit period, a code bit number in binary form corresponding to the code bit in said sequence to be produced, and for cycling said number therethrough during each code bit period; and control means coupled to said first and second means for utilizing the contents of parts thereof during each of said m clock periods, defined by said clock means to provide at the end of each code bit period a code bit in said n-bit code word, as a function of the data word and the binary representation of the code bit number in said second means.
Claim 2
Dependent Claim
173 words
An encoder of the type for converting an m-bit data word into a corresponding n-bit code word herein n 2 (m 1), 1), the encoder 2 clock means for defining m clock periods during each of a sequence of n code bit periods; first means for storing said m-bit data word and for cycling said data word therethrough during the m clock periods of each code bit period; second means for storing, during each code bit period, a code bit number in binary form corresponding to the code bit in said sequence to be produced, and for cycling said number therethrough during each code bit period; and control means coupled to said first and second means for utilizing the contents of parts thereof during each of said m clock periods, defined by said clock means to provide at the end of each code bit period a code bit in said n-bit code word, as a function of the data word and the binary representation of the code bit number in said second means.
Claim 3
Dependent Claim
27 words
The encoder as recited in claim 1 wherein said second means comprises a shift register of m-1 stages and said first means comprises and m-stage shift register.
Claim 4
Dependent Claim
47 words
The encoder as recited in claim 2 wherein said control means includes a single bistable element whose output at the end of each code bit period is either a logic one or a logic zero representing the code bit at the end of each code bit period.
Claim 5
Dependent Claim
59 words
The encoder as recited in claim 3 wherein said control means includes a plurality of gating means, responsive to the binary states of the least significant stages of the shift registers of said first and second means during at least some of the clock periods of each code bit periods for controlling the state of said single bistable element.
Claim 6
Dependent Claim
98 words
The encoder as recited in claim 4 wherein m 6, n 32, and said code bit period sequence includes periods O through 31 with said second means storing an 0 through 31 in binary form in the 5-stage shift register of said second means during the code bit periods 0 through 31 respectively, with said control means responding during each of the clock periods of each code bit period to at least the state of the least significant stage of said first means shift register to control the state of said single bistable element as a function thereof.
Claim 7
Dependent Claim
44 words
The encoder as recited in claim 5 wherein said control means include means for performing modulo-2 summation on from one to five of the data word bits for controlling the final state of said bistable element at the end of each code bit period.
Claim 8
Dependent Claim
125 words
The encoder as recited in claim 6 wherein the six data word bits are definable as a- f, a, being the least significant bit, and said control means incorporate in the modulo-2 summation said bit a, during all even-numbered code bit periods, said b bit for the first two of each group of four code bit periods, the first group starting with period 0, said c bit during the first four of each group of eight code bit periods, said d bit during the first eight of both groups of 16 code bit periods, said e bit during the first 15 code bit periods 0-15, and said f bit during each code bit period whose number in binary form includes an even number of zeros.
Claim 9
Dependent Claim
99 words
The encodEr as recited in claim 4 further including generating means for generating during each of said code bit periods 0-31 a different bit of a preselected 32-bit code word, and means for logically combining, at the end of each code bit period, the code bits from said generating means and said single bistable element. The encoder as recited in claim 8 wherein said control means include means for performing modulo-2 summation on from one to five of the data word bits for controlling the final state of said bistable element at the end of each code bit period.
Claim 10
Dependent Claim
125 words
The encoder as recited in claim 9 wherein the six data word bits are definable as a- f, a being the least significant bit, and said control means incorporate in the modulo-2 summation said bit a, during all even-numbered code bit periods, said b bit for the first two of each group of four code bit periods, the first group starting with period 0, said c bit during the first four of each group of eight code bit periods, said d bit during the first eight of both groups of 16 code bit periods, said e bit during the first 15 code bit periods 0-15, and said f bit during each code bit period whose number in binary form includes an even number of zeros.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-08 | 1974-09-07 | 1975-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-08 | 1978-09-07 | 1979-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-08 | 1982-09-07 | 1983-03-09 | $7700.00 | Window Closed / Lapsed |