US3569945A
Expired / Lapsed
US
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Low power semiconductor diode signal storage device
Assignee: International Business Machines Corp
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Filing: 1969-01-06
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Granted: 1971-03-09
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Expires: 1989-01-06
Abstract
Abstract A PNPN semiconductor diode is connected in series with an additional PN diode to form a bit memory. A bit is stored on the PNPN device by applying a positive voltage sufficiently large to break down the center junction of the PNPN device and increase the minority carriers in the regions adjacent to the center junction. Repetitive small positive voltage pulses maintain the minority carrier condition as a bit memory. A large negative voltage erases the memory cell.
Inventors
- 👤 Irving T Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/36
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
174 words
A low-power semiconductor signal storage system comprising: a. a two-terminal semiconductor device having four sequential regions of alternating conductivity types connected between said two terminals, said device having an inherently determined breakdown voltage; b. means for applying between said two terminals a pulse of input voltage at least as large as said breakdown voltage and having a polarity arranged to cause the creation of a substantial concentration of minority carriers in the middle two of said sequential regions of alternating conductivity; c. means for applying a train of periodic voltage pulses between said two terminals, wherein each of said periodic voltage pulses has an amplitude less than said breakdown voltage, has a polarity arranged to cause periodic restoration of said concentration of minority carriers to eliminate the effects of carrier density decay, and has a pulse duration less than the interval between pulses; and d. means for applying between said two terminals a pulse of erasing voltage having a magnitude and polarity arranged to cause a rapid decay in said concentration of minority carriers.
Claim 2
Dependent Claim
174 words
A low-power semiconductor signal storage system comprising: a. a two-terminal semiconductor device having four sequential regions of alternating conductivity types connected between said two terminals, said device having an inherently determined breakdown voltage; b. means for applying between said two terminals a pulse of input voltage at least as large as said breakdown voltage and having a polarity arranged to cause the creation of a substantial concentration of minority carriers in the middle two of said sequential regions of alternating conductivity; c. means for applying a train of periodic voltage pulses between said two terminals, wherein each of said periodic voltage pulses has an amplitude less than said breakdown voltage, has a polarity arranged to cause periodic restoration of said concentration of minority carriers to eliminate the effects of carrier density decay, and has a pulse duration less than the interval between pulses; and d. means for applying between said two terminals a pulse of erasing voltage having a magnitude and polarity arranged to cause a rapid decay in said concentration of minority carriers.
Claim 3
Dependent Claim
28 words
A system according to claim 1 wherein said erasing voltage is approximately equal in magnitude to said breakdown voltage and is opposite in polarity to said input voltage.
Claim 4
Dependent Claim
14 words
A system according to claim 1 wherein said semiconductor device is a PNPN diode.
Claim 5
Dependent Claim
22 words
A system according to claim 3 further comprising means for decreasing the ratio of said pulse duration to said interval between pulses.
Claim 6
Dependent Claim
24 words
A system according to claim 4 wherein said means for decreasing said ratio is a PN diode connected in series with said PNPN diode.
Claim 7
Dependent Claim
23 words
A system according to claim 3 further comprising means for determining whether or not said PNPN diode is in a substantially conductive condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-08 | 1974-09-07 | 1975-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-08 | 1978-09-07 | 1979-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-08 | 1982-09-07 | 1983-03-09 | $7700.00 | Window Closed / Lapsed |