Phase-lock loop with tangent function phase comparator

Claim 2

In a phase comparator apparatus wherein an output signal approximating the form (1k) sin phi /1+k cos phi is provided in response to a first input signal of the form A sin ( omega 1 t + Theta 1) and a second input signal of the form A cos ( omega 2 t + Theta 2), where K is a constant and phi Theta 1 - 2, the combination comprising: a. means responsive to a receiving said first and second input signals for providing a first output signal approximating the form sin phi and a second output signal approximating the form cos phi ; b. means responsive to and connecting to said first output signal for multiplying said signal by (1+k) to provide a signal approximating the form y (1+k) sin phi ; c. means responsive to and connecting to said second output signal for multiplying said signal by k to provide a signal approximating the form x k cos phi ; d. means responsive to and connecting to said signal x k cos phi for providing an output signal that is a nonlinear function of said signal x, said output signal approximating the form e. means responsive to and connecting to said y and z signals for providing an output signal proportional to the product of said y and z signals, said output signal approximating the form (1+k) sin phi /1+k cos phi .

Claim 3

The combination according to claim 1 wherein said nonlinear means comprises means having a transfer function that is substantially exponential.

Claim 4

voltage controlled means responsive to and connecting to said phase comparator output signal for providing an output signal having a frequency and phase that is a function of the voltage magnitude of said phase comparator output signal; and

Claim 5

voltage controlled means responsive to and connecting to said phase comparator output signal for providing an output signal having a frequency and phase that is a function of the voltage magnitude of said phase comparator output signal; and

Claim 6

voltage controlled means responsive to and connecting to said phase comparator output signal for providing an output signal having a frequency and phase that is a function of the voltage magnitude of said phase comparator output signal

Claim 7

voltage controlled means responsive to and connecting to said phase comparator output signal for providing an output signal having a frequency and phase that is a function of the voltage magnitude of said phase comparator output signal

Claim 8

voltage-controlled means responsive to and connecting to said phase comparator output signal for providing an output signal having a frequency and phase that is a function of the voltage magnitude of said phase comparator output signal;

Claim 9

voltage-controlled means responsive to and connecting to said phase comparator output signal for providing an output signal having a frequency and phase that is a function of the voltage magnitude of said phase comparator output signal;

Claim 10

means responsive to and connecting to said voltage-controlled means output for frequency doubling said signal,

Claim 11

means responsive to and connecting to said voltage-controlled means output for frequency doubling said signal,

Claim 12

means for applying said voltage controlled means output to said phase comparator as said second input signal;

Claim 13

means for applying said voltage controlled means output to said phase comparator as said second input signal;

Claim 14

means for applying said voltage controlled means output signal to said phase comparator as said second signal, whereby said second signal is substantially in frequency and phase coherence with said first signal when the phase-lock loop is in lock.

Claim 15

means for applying said voltage controlled means output signal to said phase comparator as said second signal, whereby said second signal is substantially in frequency and phase coherence with said first signal when the phase-lock loop is in lock.

Claim 16

The combination according to claim 2 wherein said exponential function means includes a PN junction and means to bias said junction to provide a substantially exponential transfer characteristic.

Claim 17

In a phase-lock loop apparatus including a phase comparator having an output signal approximating the form (1+k) sin phi /1+k cos phi in response to the first input signal of the form A sin ( omega 1 t + Theta 1) and a second input signal of the form A cos ( omega 2 t Theta 2), where k is a constant and phi Theta 1 - Theta 2, the combination comprising:

Claim 18

In a phase-lock loop apparatus including a phase comparator having an output signal approximating the form (1+k) sin phi /1+k cos phi in response to the first input signal of the form A sin ( omega 1 t + Theta 1) and a second input signal of the form A cos ( omega 2 t Theta 2), where k is a constant and phi Theta 1 - Theta 2, the combination comprising:

Claim 19

means responsive to and receiving said received digital pulses for providing an output signal that is differentiated digital pulses;

Claim 20

means responsive to and receiving said received digital pulses for providing an output signal that is differentiated digital pulses;

Claim 21

means for applying said frequency doubled voltage-controlled means output signal to said phase comparator as said second signal;

Claim 22

means for applying said frequency doubled voltage-controlled means output signal to said phase comparator as said second signal;

Claim 23

In a carrier recovery loop apparatus for providing a carrier signal in frequency and phase coherence with an input signal, said input signal characterized by a modulated carrier and noise, said apparatus including a phase-lock loop having a phase comparator of the type having an output signal approximating the form (1+k) sin phi /1+k cos phi is provided in response to a first input signal of the form A sin ( omega 1 t + Theta 1) and a second input signal of the form A cos ( omega 2 t + Theta 2), where k is a constant and phi Theta 1 31 Theta 2, the combination comprising: 1. a phase comparator comprising: a. means responsive to and receiving said first and second input signals for providing a first output signal approximating the form sin phi and a second output signal approximating the form cos phi . b. means responsive to and connecting to said first output signal for multiplying said signal by (1+k) to provide a signal approximating the form y (1+k) sin phi , c. means responsive to and connecting to said second output signal for multiplying said signal by k to provide a signal approximating the form x k cos phi , d. means responsive to and connecting to said signal y k cos phi for providing an output signal that is a nonlinear function of said signal x, said output signal approximating the form e. means responsive to and connecting to said y and z signals for providing an output signal proportional to the product of said y and z signals; said output signal approximating the form (1+k) sin phi /1+k cos phi .

Claim 24

In a carrier recovery loop apparatus for providing a carrier signal in frequency and phase coherence with an input signal, said input signal characterized by a modulated carrier and noise, said apparatus including a phase-lock loop having a phase comparator of the type having an output signal approximating the form (1+k) sin phi /1+k cos phi is provided in response to a first input signal of the form A sin ( omega 1 t + Theta 1) and a second input signal of the form A cos ( omega 2 t + Theta 2), where k is a constant and phi Theta 1 31 Theta 2, the combination comprising: 1. a phase comparator comprising: a. means responsive to and receiving said first and second input signals for providing a first output signal approximating the form sin phi and a second output signal approximating the form cos phi . b. means responsive to and connecting to said first output signal for multiplying said signal by (1+k) to provide a signal approximating the form y (1+k) sin phi , c. means responsive to and connecting to said second output signal for multiplying said signal by k to provide a signal approximating the form x k cos phi , d. means responsive to and connecting to said signal y k cos phi for providing an output signal that is a nonlinear function of said signal x, said output signal approximating the form e. means responsive to and connecting to said y and z signals for providing an output signal proportional to the product of said y and z signals; said output signal approximating the form (1+k) sin phi /1+k cos phi .

Claim 25

means responsive to and receiving said input signal for frequency doubling said signal; and

Claim 26

means responsive to and receiving said input signal for frequency doubling said signal; and

Claim 27

means responsive to and connecting to said differentiated means output signal for full-wave rectifying said signal to provide an output signal; and

Claim 28

means responsive to and connecting to said differentiated means output signal for full-wave rectifying said signal to provide an output signal; and

Claim 29

means for applying said full-wave rectifying means output signal to said phase comparator as said first input signal whereby said voltage-controlled means output signal is a pulse train in synchronism with the timing of said received digital pulses when said phase-lock loop is in lock.

Claim 30

means for applying said full-wave rectifying means output signal to said phase comparator as said first input signal whereby said voltage-controlled means output signal is a pulse train in synchronism with the timing of said received digital pulses when said phase-lock loop is in lock.

Claim 31

In a bit-timing recovery loop apparatus for providing a pulse train in synchronism with the timing of received digital pulses, said apparatus including a phase-lock loop having a phase comparator of the type having an output signal approximating the form (1+k) sin phi /1+k cos phi in response to a first input signal of the form A sin ( omega 2 t + Theta 2), and a second input signal of the form A cos( Theta 2 t + Theta 2), where k is a constant and phi - Theta 2, the combination comprising:

Claim 32

In a bit-timing recovery loop apparatus for providing a pulse train in synchronism with the timing of received digital pulses, said apparatus including a phase-lock loop having a phase comparator of the type having an output signal approximating the form (1+k) sin phi /1+k cos phi in response to a first input signal of the form A sin ( omega 2 t + Theta 2), and a second input signal of the form A cos( Theta 2 t + Theta 2), where k is a constant and phi - Theta 2, the combination comprising:

Claim 33

means for applying said frequency doubled input signal to said phase comparator as said first signal whereby said voltage-controlled means output is a carrier signal substantially in frequency and phase coherence with said input signal when said phase-lock loop is lock.

Claim 34

means for applying said frequency doubled input signal to said phase comparator as said first signal whereby said voltage-controlled means output is a carrier signal substantially in frequency and phase coherence with said input signal when said phase-lock loop is lock.