High speed nonsaturating logic circuit

Claim 1

An integrated nonsaturating emitter-coupled gate circuit comprising: a first output transistor; a bias transistor; conductor means connecting the collector of the bias transistor to the base of said first output transistor; a first load resistance connecting the base of the first output transistor to a DC supply; a second output transistor; conductor means connecting the base of the second output transistor to the collectors of a plurality of input transistors in parallel, all of said transistors being of the same polarity and having a diode characteristic exhibiting a slope change for a forward bias voltage v , a second load resistance connecting the base of the second output transistor to said DC supply; a common input resistance connecting the other polarity of said DC supply to the emitters of all input transistors and of the bias transistor; a clamping diode located in parallel with said second load resistance for clamping the base voltage of the second output transistor when the latter is in conductive condition thereof, wherein said supply provides a voltage substantially equal to 3 v and said common input resistance has a value which corresponds to a logical swing equal to v; a power supply common to a plurality of said circuits comprising a supply voltage stablilizing ballast consisting of a chain of four diodes in series relation and having a characteristic exhibiting a slope change for said voltage v and a transistor also having a diode characteristic exhibiting a slop change for said voltage v,the base of said last named transistor being connected to one end of said chain; and means for applying a voltage higher than 4v across the collector of said last named transistor and the other end of said chain whereby said DC supply is available between said other end and the emitter of said last named transistor.