US3569731A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage level detector
Assignee: United States Department of the Air Force
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Filing: 1968-08-20
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Granted: 1971-03-09
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Expires: 1988-08-20
Abstract
Abstract The invention comprises a voltage level detector having a ''''dead band'''' between its set and reset points. The critical level or significant end of the dead band is desensitized to temperature variations and drift by positive and negative feedback in combination with a circuit adapted to compensate for variations of the voltage amplifier transistor transconductance. Significant system components include a feedback circuit between the detector''s differential amplifier and voltage amplifier, a temperature compensation circuit associated with the voltage amplifier, and a time delay circuit. The invention also comprehends a voltage monitoring system employing three such voltage level detectors in combination with a ''''majority voting'''' logic circuit.
Inventors
- 👤 Horacio E Gavira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:45
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/25; H; H03; H03G; H03G11/00; H03G11/002; H03K; H03K19/00; H03K19/02; H03K19/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
435 words
A voltage level detector comprising: terminal means for connection to a voltage source to be monitored; ground means; an energy storage circuit having an output bus; first and second resistors connected in series between said terminal means and said ground means; a differential amplifier comprising first and second NPN transistors, the emitters of said NPN transistors being connected to said ground means through a third resistor, the collector of said first NPN transistor being connected to said terminal means through a fourth resistor, the collector of said second NPN transistor being connected to said terminal means through series connected fifth and sixth resistors, the base of said first NPN transistor being connected to the junction of said first and second resistors, and the base of said second NPN transistor being connected to said energy storage bus through series connected seventh and eighth resistors; a voltage amplifier comprising first and second PNP transistors, the emitter of said PNP transistors being connected to said terminal means, ninth and tenth resistors connected in series between said terminal means and the collector of said first PNP transistor, means connecting the base of said first PNP transistor to the junction of said fifth and sixth resistors, means connecting the base of said second PNP transistor to the junction of said ninth and tenth resistors, eleventh and twelfth resistors connected in series between the base of said first PNP transistor and the base of said second NPN transistor, a thirteenth resistor connected to the collector of said first PNP transistor, a first diode connected between said thirteenth resistor and said ground means, means connecting the collector of said first PNP transistor to the junction Of said eleventh and twelfth resistors, fourteenth and fifteenth resistors connected in series relationship between the junction of said first diode and said thirteenth resistor and said ground means, a first capacitor connected between the base of said first NPN transistor and said ground means, a second diode connected between the emitter and the base of said first NPN transistor, a Zener diode connected between the junction of said fourteenth and fifteenth resistors and the junction of said seventh and eighth resistors; an output circuit comprising the series arrangement of a sixteenth resistor connected to the collector of said second PNP transistor, a third diode connected to said sixteenth resistor and a seventeenth resistor connected to said third diode, and a time delay circuit comprising a second condensor connected between the junction of said third diode and said seventeenth resistor and said ground means, and an eighteenth resistor connected between said seventeenth resistor and said ground means.
Claim 2
Dependent Claim
435 words
A voltage level detector comprising: terminal means for connection to a voltage source to be monitored; ground means; an energy storage circuit having an output bus; first and second resistors connected in series between said terminal means and said ground means; a differential amplifier comprising first and second NPN transistors, the emitters of said NPN transistors being connected to said ground means through a third resistor, the collector of said first NPN transistor being connected to said terminal means through a fourth resistor, the collector of said second NPN transistor being connected to said terminal means through series connected fifth and sixth resistors, the base of said first NPN transistor being connected to the junction of said first and second resistors, and the base of said second NPN transistor being connected to said energy storage bus through series connected seventh and eighth resistors; a voltage amplifier comprising first and second PNP transistors, the emitter of said PNP transistors being connected to said terminal means, ninth and tenth resistors connected in series between said terminal means and the collector of said first PNP transistor, means connecting the base of said first PNP transistor to the junction of said fifth and sixth resistors, means connecting the base of said second PNP transistor to the junction of said ninth and tenth resistors, eleventh and twelfth resistors connected in series between the base of said first PNP transistor and the base of said second NPN transistor, a thirteenth resistor connected to the collector of said first PNP transistor, a first diode connected between said thirteenth resistor and said ground means, means connecting the collector of said first PNP transistor to the junction Of said eleventh and twelfth resistors, fourteenth and fifteenth resistors connected in series relationship between the junction of said first diode and said thirteenth resistor and said ground means, a first capacitor connected between the base of said first NPN transistor and said ground means, a second diode connected between the emitter and the base of said first NPN transistor, a Zener diode connected between the junction of said fourteenth and fifteenth resistors and the junction of said seventh and eighth resistors; an output circuit comprising the series arrangement of a sixteenth resistor connected to the collector of said second PNP transistor, a third diode connected to said sixteenth resistor and a seventeenth resistor connected to said third diode, and a time delay circuit comprising a second condensor connected between the junction of said third diode and said seventeenth resistor and said ground means, and an eighteenth resistor connected between said seventeenth resistor and said ground means.
Claim 3
Dependent Claim
350 words
A voltage level detector comprising: terminal means for connection to a voltage source to be monitored; ground means; a first resistance connected to said terminal means, a first diode connected to said first resistance and a second resistance connected between said first diode and said ground means; a differntial amplifier comprising first and second NPN transistors, the emitters of said NPN transistors being connected to said ground means through a third resistor, the collector of said first NPN transistor being connected to said terminal means through series-connected fourth and fifth resistors, the collector of said second NPN transistor being connected to said terminal means through a sixth resistor; seventh and eighth resistors arranged in series relationship and connected in parallel with said first diode; means connecting the base of said first NPN transistor to the junction of said seventh and eighth resistors; a first capacitor connected between the base of said first NPN transistor and said ground means; a ninth resistor connected to terminal means; a zener diode connected between said ninth resistor and said ground means; means connecting the base of said second NPN transistor to the junction of said Zener diode and said ninth resistor; a voltage amplifier comprising a PNP transistor, the emitter thereof being connected to said terminal means, and the base thereof being connected to the junction of said fourth and fifth resistors; a tenth resistor connected between the collector of said PNP transistor and said ground means; an eleventh resistor connected between the collector and the base of said PNP transistor; a twelfth resistor connected between the collector of said PNP transistor and the base of said first NPN transistor; a thirteenth resistor connected to the collector of said first PNP transistor; a second diode connected to said thirteenth resistor; a second capacitor connected between said diode and said ground means; a fourteenth resistor connected between the junction of said second diode and said second capacitor and said ground means; and an output circuit, said output circuit being connected to the junction of said second diode and said second capacitor through a fifteenth resistor.
Claim 4
Dependent Claim
350 words
A voltage level detector comprising: terminal means for connection to a voltage source to be monitored; ground means; a first resistance connected to said terminal means, a first diode connected to said first resistance and a second resistance connected between said first diode and said ground means; a differntial amplifier comprising first and second NPN transistors, the emitters of said NPN transistors being connected to said ground means through a third resistor, the collector of said first NPN transistor being connected to said terminal means through series-connected fourth and fifth resistors, the collector of said second NPN transistor being connected to said terminal means through a sixth resistor; seventh and eighth resistors arranged in series relationship and connected in parallel with said first diode; means connecting the base of said first NPN transistor to the junction of said seventh and eighth resistors; a first capacitor connected between the base of said first NPN transistor and said ground means; a ninth resistor connected to terminal means; a zener diode connected between said ninth resistor and said ground means; means connecting the base of said second NPN transistor to the junction of said Zener diode and said ninth resistor; a voltage amplifier comprising a PNP transistor, the emitter thereof being connected to said terminal means, and the base thereof being connected to the junction of said fourth and fifth resistors; a tenth resistor connected between the collector of said PNP transistor and said ground means; an eleventh resistor connected between the collector and the base of said PNP transistor; a twelfth resistor connected between the collector of said PNP transistor and the base of said first NPN transistor; a thirteenth resistor connected to the collector of said first PNP transistor; a second diode connected to said thirteenth resistor; a second capacitor connected between said diode and said ground means; a fourteenth resistor connected between the junction of said second diode and said second capacitor and said ground means; and an output circuit, said output circuit being connected to the junction of said second diode and said second capacitor through a fifteenth resistor.
Claim 5
Dependent Claim
260 words
A voltage monitoring system comprising three voltage level detector circuits, each said detector circuit comprising terminal means for connection to a voltage to be monitored, ground means, a differential amplifier connected between said terminal means and said ground means, a stable voltage source connected between said ground means, said terminal means and said differential amplifier, voltage amplifier means connected to the output of said differential amplifier, a feedback circuit connected between said voltage amplifier means and said differential amplifier, said feedback means being adapted to fix the gain of saId voltage amplifier means, a temperature compensation circuit connected between said voltage amplifier means and ground, a time delay circuit connected to the output of said voltage amplifier means, and output means connected to said time delay circuit, first and second diodes connected in series relationship between the output of said first voltage level detector and the output of said third voltage level detector, third and fourth diodes connected in series relationship between the output of said second voltage level detector and the output of said first voltage level detector, fifth and sixth diodes connected in series relationship between the output of said third voltage level detector and the output of said second voltage level detector, an output terminal, a seventh diode connected between the junction of said first and second diodes and said output terminal, an eighth diode connected between the junction of said third and fourth diodes and said output terminal, and a ninth diode connected between the junction of said fifth and sixth diode and said output terminal.
Claim 6
Dependent Claim
260 words
A voltage monitoring system comprising three voltage level detector circuits, each said detector circuit comprising terminal means for connection to a voltage to be monitored, ground means, a differential amplifier connected between said terminal means and said ground means, a stable voltage source connected between said ground means, said terminal means and said differential amplifier, voltage amplifier means connected to the output of said differential amplifier, a feedback circuit connected between said voltage amplifier means and said differential amplifier, said feedback means being adapted to fix the gain of saId voltage amplifier means, a temperature compensation circuit connected between said voltage amplifier means and ground, a time delay circuit connected to the output of said voltage amplifier means, and output means connected to said time delay circuit, first and second diodes connected in series relationship between the output of said first voltage level detector and the output of said third voltage level detector, third and fourth diodes connected in series relationship between the output of said second voltage level detector and the output of said first voltage level detector, fifth and sixth diodes connected in series relationship between the output of said third voltage level detector and the output of said second voltage level detector, an output terminal, a seventh diode connected between the junction of said first and second diodes and said output terminal, an eighth diode connected between the junction of said third and fourth diodes and said output terminal, and a ninth diode connected between the junction of said fifth and sixth diode and said output terminal.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-08 | 1974-09-07 | 1975-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-08 | 1978-09-07 | 1979-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-08 | 1982-09-07 | 1983-03-09 | $7700.00 | Window Closed / Lapsed |