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US3569678A Expired / Lapsed US ⏱️ 0.0 years remaining

Static counter

Assignee: Bolkow GmbH
•
Filing: 1967-04-28
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Granted: 1971-03-09
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Expires: 1987-04-28
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Abstract

Abstract A static counter for forward and backward counting comprises a plurality of counting stages each of which includes a prestorage portion and a main storage portion. In advance of the counter for the first binary digit, there is connected an input gate circuit which indicates any change of state of the counting signal for the first binary digit, that is, whether the counting is to be changed from forward to backward or vice versa. The binary digit stages succeeding the first binary digit stage are controlled by the storage state of the respective immediately preceding counting stage.

Inventors

  • 👤 Gunter Emde

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 05:25
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/56

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 189 words
A static counter for forward and backward counting with selective presetting, comprising, in combination, a plurality of counting stages each having a prestorage and a main storage indicating the counting result of a respective binary digit; a switching stage associated with the first binary digit and providing an indication of each change of state of a counting signal applied to its input; said counting stages being connected serially to each other with the first counting stage being connected to the output of said switching stage; means connecting the storages of each counting stage to inputs of the respective next succeeding counting stage and operable to control the continued counting and the counting direction of such respective next succeeding counting stage in accordance with the switching states of the storages of the respective immediately preceding counting stage; counting direction signal means connected to inputs of only said first counting stage and applying counting direction signals to the latter; and counting signal means connecting said switching stage to inputs of only said first counting stage and controlling counting of the latter in accordance with the counting state of said switching stage.
Claim 2
Dependent Claim 189 words
A static counter for forward and backward counting with selective presetting, comprising, in combination, a plurality of counting stages each having a prestorage and a main storage indicating the counting result of a respective binary digit; a switching stage associated with the first binary digit and providing an indication of each change of state of a counting signal applied to its input; said counting stages being connected serially to each other with the first counting stage being connected to the output of said switching stage; means connecting the storages of each counting stage to inputs of the respective next succeeding counting stage and operable to control the continued counting and the counting direction of such respective next succeeding counting stage in accordance with the switching states of the storages of the respective immediately preceding counting stage; counting direction signal means connected to inputs of only said first counting stage and applying counting direction signals to the latter; and counting signal means connecting said switching stage to inputs of only said first counting stage and controlling counting of the latter in accordance with the counting state of said switching stage.
Claim 3
Dependent Claim 17 words
A static counter, as claimed in claim 1, in which said switching stage is an input gate-circuit.
Claim 4
Dependent Claim 45 words
A static counter, as claimed in claim 2, including a zero setting input connected to said input gate-circuit and operable to set the latter so that each state of the counting signal can be processed selectively either as an O or as an L signal.
Claim 5
Dependent Claim 28 words
A static counter, as claimed in claim 3, including means connecting said zero setting input to inputs of each of said counting stages for resetting of the latter.
Claim 6
Dependent Claim 48 words
A static counter, as claimed in claim 2, in which said counting direction signal means comprises counting direction signal lines connected to counting signal inputs; and delay means incorporated in each counting direction signal line between said counting signal inputs and the inputs of said first counting stage.
Claim 7
Dependent Claim 33 words
A static counter, as claimed in claim 5, including means connecting said input gate-circuit to said counting signal inputs and operable to suppress the initial counting increment following each change of counting direction.
Claim 8
Dependent Claim 22 words
A static counter, as claimed in claim 1, in which said switching stage and each of said counting stages comprise NAND members.
Claim 9
Dependent Claim 97 words
A static counter, as claimed in claim 1, in which the internal circuit connections of said first counting stage have a configuration such that the following equations of Boolian algebra are satisfied: the states at the setting inputs of the main storage, Z01 and Z01 indicate the states of the outputs of the prestorage, Z1 and Z1 indicate the states of the outputs of the main storage, R and R indicate the counting direction signals and Z0 and Z0 indicate the states of the outputs of said switching stage connected to inputs of said first counting stage.
Claim 10
Dependent Claim 114 words
A static counter, as claimed in claim 8, in which the internal circuitry of all of the counting stages except said first counting stage have a configuration such that the following equations of Boolian algebra are satisfied: and wherein Z01 and Z01 indicate the states of the outputs of the prestorage of each succeeding counting stage, Zi and Zi indicate the states of the outputs of the main storage of each succeeding counting stage, ZO.i 1 and ZO.i 1 indicate the states of the outputs of the prestorage of each succeeding counting stage and Zi-1 and Zi-1 indicate the states of the outputs of the main storage of the respective immediately preceding counting stage.

References Cited (Backward Citations)

US3114883A Cited
US3414719A Cited
US3356953A Cited
US3443071A Cited
US3354295A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-03-08 1974-09-07 1975-03-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-03-08 1978-09-07 1979-03-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-03-08 1982-09-07 1983-03-09 $7700.00 Window Closed / Lapsed

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