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US3568095A Expired / Lapsed US ⏱️ 0.0 years remaining

Self-balancing modulator for suppression of carrier wave

Assignee: Italtel SpA
•
Filing: 1968-10-16
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Granted: 1971-03-02
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Expires: 1988-10-16
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Abstract

Abstract Two transistors of opposite conductivity types are connected back-to-back, with their emitters confronting each other, across a source of DC driving voltage for push-pull energization by a carrier wave and parallel energization by an applied low frequency modulating signal. A condenser connected to the junction of the two emitter leads differentially biases the transistors to compensate for unsymmetrical conductivity.

Inventors

  • 👤 Giovanni Cordalis

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 06:55
CPC Classifications
H; H03; H03C; H03C1/00; H03C1/52; H03C1/54; H03C1/542; H03C1/545

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 209 words
A circuit arrangement for modulating a carrier wave with a low frequency signal and preserving the resulting sidebands while suppressing the carrier wave, comprising: a first pair of terminals connectable across a source of carrier wave to be modulated; a second pair of terminals connectable across a source of modulating signal; a third pair of terminals connectable across a load; a fourth pair of terminals connectable across a source of direct current; two transistors of opposite conductivity types each having a base, an emitter with a lead and a collector, the emitter leads of said transistors forming a junction, the emitter-collector paths of said transistors being serially connected across said fourth pair of terminals in aiding relationship; first circuit means coupling said first pair of terminals in push-pull (parallel) to the base-emitter paths of said transistors; second circuit means coupling said second pair of terminals in parallel to the base-emitter paths of said transistors, said second circuit means including capacitive means connected to said junction for differentIally biasing the emitters of said transistors in response to unsymmetrical current flow over said emitter-collector paths; and and third circuit means coupling said third pair of terminals to said emitter-collector paths for balanced energization thereby in the absence of said modulating signal.
Claim 2
Dependent Claim 209 words
A circuit arrangement for modulating a carrier wave with a low frequency signal and preserving the resulting sidebands while suppressing the carrier wave, comprising: a first pair of terminals connectable across a source of carrier wave to be modulated; a second pair of terminals connectable across a source of modulating signal; a third pair of terminals connectable across a load; a fourth pair of terminals connectable across a source of direct current; two transistors of opposite conductivity types each having a base, an emitter with a lead and a collector, the emitter leads of said transistors forming a junction, the emitter-collector paths of said transistors being serially connected across said fourth pair of terminals in aiding relationship; first circuit means coupling said first pair of terminals in push-pull (parallel) to the base-emitter paths of said transistors; second circuit means coupling said second pair of terminals in parallel to the base-emitter paths of said transistors, said second circuit means including capacitive means connected to said junction for differentIally biasing the emitters of said transistors in response to unsymmetrical current flow over said emitter-collector paths; and and third circuit means coupling said third pair of terminals to said emitter-collector paths for balanced energization thereby in the absence of said modulating signal.
Claim 3
Dependent Claim 20 words
A circuit arrangement as defined in claim 1 wherein said leads include respective resistors between said junction and said emitters.
Claim 4
Dependent Claim 58 words
A circuit arrangement as defined in claim 1, further comprising a voltage divider connected across said fourth pair of terminals, the bases of said transistors being connected to respective taps on said voltage divider, said second circuit means further including a capacitive connection between one of said second pair of terminals and the midpoint of said voltage divider.
Claim 5
Dependent Claim 28 words
A circuit arrangement as defined in claim 3 wherein said first circuit means includes a pair of condensers respectively coupling said taps to said first pair of terminals.
Claim 6
Dependent Claim 17 words
A circuit arrangement as defined in claim 1 wherein said third circuit means includes an output transformer.
Claim 7
Dependent Claim 17 words
A circuit arrangement as defined in claim 1 wherein said first circuit means includes an input transformer.
Claim 8
Dependent Claim 35 words
A circuit arrangement as defined in claim 6 wherein said input transformer has a balanced secondary with a center tap connected to a terminal of each of said second, third and fourth pairs of terminals.

References Cited (Backward Citations)

US2788493A Cited
US3101455A Cited
US3305796A Cited
US3160766A Cited
US3381234A Cited
US3434066A Cited
US3484723A Cited
US3461320A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-03-01 1974-08-31 1975-03-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-03-01 1978-08-31 1979-03-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-03-01 1982-08-31 1983-03-02 $7700.00 Window Closed / Lapsed

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