US3568066A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency multiple differential phase modulation signal receiver
Assignee: Fujitsu Ltd
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Filing: 1968-07-05
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Granted: 1971-03-02
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Expires: 1988-07-05
Abstract
Abstract First and second phase detectors detect the phase of the input signal and utilize a first demodulating reference signal and a second reference signal having a phase difference of 90* from the first reference signal. A first integrator is connected to the first phase detector and a second integrator is connected to the second phase detector. A sampling circuit connected to the first and second integrators samples the outputs thereof and shapes the waveforms of the output. A signal generator generates a single reference signal. Third and fourth phase detectors detect the phase of the input signal utilizing the single reference signal and a fourth reference signal having a phase difference of 90* from the single reference signal. A third integrator is connected to the third phase detector and a fourth integrator is connected to the fourth phase detector. A first holding circuit is connected to the third integrator and a second holding circuit is connected to the fourth integrator. Each holding circuit holds a signal for a determined period. A first modulator connected to the first holding circuit modulates the output signals thereof with the single reference signal. A second modulation connected to the second holding circuit modulates the output signals thereof with the fourth reference signal. A combining circuit connected between the first and second modulators and each of the first and second phase detectors combines the output signals of the modulators.
Inventors
- 👤 Noriaki Fujimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:12
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/02; H04L5/06
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
503 words
A frequency multiple differential phase modulation signal receiver, comprising: input means for supplying a received input signal; reference signal means for providing a first demodulating reference signal and a second reference signal having a phase difference of 90* from said first demodulating reference signal; a demodulating circuit for demodulating the received input signal, said demodulating circuit comprising first and second phase detecting circuits having inputs connected to said input means and outputs for detecting the phase of the input signal, said phase detecting circuits utilizing the first demodulating reference signal and the second reference signal, a first integrating circuit having an output and an input connected to the output of said first phase detecting circuit and a second integrating circuit having an outpUt and an input connected to the output of said second phase detecting circuit, and a sampling circuit having inputs connected to the outputs of said first and second integrating circuits for sampling the outputs of said integrating circuits and shaping the waveforms of said outputs; reference signal means for providing a fourth reference signal having a phase difference of 90* from the single reference signal; and a demodulating reference signal circuit comprising signal generating means having an output for generating a single reference signal, third and fourth phase detecting circuits having inputs connected to said input means and outputs for detecting the phase of the input signal, said third and fourth phase detecting circuits utilizing the single reference signal and the fourth reference signal, a third integrating circuit having an output and an input connected to the output of said third phase detecting circuit and a fourth integrating circuit having an output and an input connected to the output of said fourth phase detecting circuit, a first holding circuit having an output and an input connected to the output of said third integrating circuit and a second holding circuit having an output and an input connected to the output of said fourth integrating circuit, each of said first and second holding circuits holding an integrated signal for a determined period, a first modulator having an output and an input connected to the output of said first holding circuit for modulating the output signals of said first holding circuit with the single reference signal and a second modulator having an output and an input connected to the output of said second holding circuit for modulating the output signals of said second holding circuit with the fourth reference signal, and a combining circuit having inputs connected to the outputs of said first and second modulators and the inputs of each of said first and second phase detecting circuits for combining the output signals of said modulators, said third integrating circuit and said first holding circuit being combined and said fourth integrating circuit and said second holding circuit being combined and each of said combined circuits comprising two integrating circuits, switch means connected to said integrating circuits and switch control means for controlling said switch means to integrate and hold signals supplied thereto.
Claim 2
Dependent Claim
503 words
A frequency multiple differential phase modulation signal receiver, comprising: input means for supplying a received input signal; reference signal means for providing a first demodulating reference signal and a second reference signal having a phase difference of 90* from said first demodulating reference signal; a demodulating circuit for demodulating the received input signal, said demodulating circuit comprising first and second phase detecting circuits having inputs connected to said input means and outputs for detecting the phase of the input signal, said phase detecting circuits utilizing the first demodulating reference signal and the second reference signal, a first integrating circuit having an output and an input connected to the output of said first phase detecting circuit and a second integrating circuit having an outpUt and an input connected to the output of said second phase detecting circuit, and a sampling circuit having inputs connected to the outputs of said first and second integrating circuits for sampling the outputs of said integrating circuits and shaping the waveforms of said outputs; reference signal means for providing a fourth reference signal having a phase difference of 90* from the single reference signal; and a demodulating reference signal circuit comprising signal generating means having an output for generating a single reference signal, third and fourth phase detecting circuits having inputs connected to said input means and outputs for detecting the phase of the input signal, said third and fourth phase detecting circuits utilizing the single reference signal and the fourth reference signal, a third integrating circuit having an output and an input connected to the output of said third phase detecting circuit and a fourth integrating circuit having an output and an input connected to the output of said fourth phase detecting circuit, a first holding circuit having an output and an input connected to the output of said third integrating circuit and a second holding circuit having an output and an input connected to the output of said fourth integrating circuit, each of said first and second holding circuits holding an integrated signal for a determined period, a first modulator having an output and an input connected to the output of said first holding circuit for modulating the output signals of said first holding circuit with the single reference signal and a second modulator having an output and an input connected to the output of said second holding circuit for modulating the output signals of said second holding circuit with the fourth reference signal, and a combining circuit having inputs connected to the outputs of said first and second modulators and the inputs of each of said first and second phase detecting circuits for combining the output signals of said modulators, said third integrating circuit and said first holding circuit being combined and said fourth integrating circuit and said second holding circuit being combined and each of said combined circuits comprising two integrating circuits, switch means connected to said integrating circuits and switch control means for controlling said switch means to integrate and hold signals supplied thereto.
Claim 3
Dependent Claim
27 words
A frequency multiple differential phase modulation signal receiver as claimed in claim 1, wherein said switch means of each of said combined circuits comprises a single switch.
Claim 4
Dependent Claim
28 words
A frequency multiple differential phase modulation signal receiver as claimed in claim 1, wherein said switch means of each of said combined circuits comprises a plurality of switches.
Claim 5
Dependent Claim
103 words
A frequency multiple differential phase modulation signal receiver as claimed in claim 1, further comprising an adding circuit connected to each of said first and second integrating circuits for adding signals supplied by said integrating circuits, a subtracting circuit connected to each of said first and second integrating circuits in parallel with said adding circuit for subtracting signals supplied by said integrating circuits, one from the other, a first sampling and shaping circuit connected to said adding circuit, a second sampling and shaping circuit connected to said subtracting circuit and OR circuit means connected to said first and second sampling and shaping circuits.
Claim 6
Dependent Claim
27 words
A frequency multiple differential phase modulation signal receiver as claimed in claim 4, wherein said switch means of each of said combined circuits comprises a single switch.
Claim 7
Dependent Claim
28 words
A frequency multiple differential phase modulation signal receiver as claimed in claim 4, wherein said switch means of each of said combined circuits comprises a plurality of switches.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |