US3567966A
Expired / Lapsed
US
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Transient suppression circuit
Assignee: Combustion Engineering Inc
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Filing: 1968-04-10
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Granted: 1971-03-02
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Expires: 1988-04-10
Abstract
Abstract Solid-state circuitry for coupling input signals of relatively long duration to a logic system, the circuitry comprising an integrator which, in response to input signals of the proper magnitude, duration and polarity, provides a ramp voltage to a level detector. Improved transient suppression is achieved by employing input signals to provide, after integration, the base and collector drive for an input transistor. The circuitry is also characterized by adjustable turn on and turn off times which may be made symmetrical if desired.
Inventors
- 👤 Lyman F Gilbert
- 👤 William W Landon Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:20
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
131 words
A transient suppression circuit comprising: an input signal-powered transistor, said transistor being normally nonconductive and without base and collector drive; means for coupling input signals to the base of said input transistor, said coupling means including an integrator circuit which presents substantially a short circuit to short duration input signAls applied thereto; Zener diode means connected across the input to said coupling means whereby said transistor will be rendered conductive only in response to input signals of long duration and a first polarity; an output terminal; and means connected between the emitter of said transistor and said output terminal for delaying the application to said output terminal of output signals provided by said transistor when it is rendered conductive in response to input signals of sufficient duration and the proper polarity.
Claim 2
Dependent Claim
131 words
A transient suppression circuit comprising: an input signal-powered transistor, said transistor being normally nonconductive and without base and collector drive; means for coupling input signals to the base of said input transistor, said coupling means including an integrator circuit which presents substantially a short circuit to short duration input signAls applied thereto; Zener diode means connected across the input to said coupling means whereby said transistor will be rendered conductive only in response to input signals of long duration and a first polarity; an output terminal; and means connected between the emitter of said transistor and said output terminal for delaying the application to said output terminal of output signals provided by said transistor when it is rendered conductive in response to input signals of sufficient duration and the proper polarity.
Claim 3
Dependent Claim
25 words
The circuit of claim 1 wherein said input transistor is connected as an emitter follower and wherein said delay means comprises a low pass filter.
Claim 4
Dependent Claim
26 words
The circuit of claim 2 wherein said filter comprises: input and output capacitors, said input capacitor having a plate connected to the emitter of said transistor.
Claim 5
Dependent Claim
20 words
The circuit of claim 3 further comprising: means for limiting the charging rate of the input capacitor of said filter.
Claim 6
Dependent Claim
28 words
The circuit of claim 4 wherein said charging rate limiting means comprises: resistance means connected between the collector of said transistor and the input of said coupling means.
Claim 7
Dependent Claim
27 words
The circuit of claim 5 wherein said delay means further comprises: level detector means connected between the output of said low pass filter and said output terminal.
Claim 8
Dependent Claim
48 words
The circuit of claim 6 wherein said level detector means comprises: a second normally nonconductive transistor, said second transistor having a grounded emitter and having its collector coupled to said output terminal; and resistance means connecting the output of said filter to the base of said second transistor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |