Counter

Claim 2

A counter for providing a sum of discrete inputs to be counted comprising: first means for counting said inputs to be counted, including carry output means for generating carries when the count in said first means reaches a predetermined level; second means for counting inputs thereto; third means for coupling said carry output means to said second means to enable said second means to count carries generated by said carry output means; clock means for generating clock pulses, said clock means coupled to said second means to provide a count therein representing the elapsed time prior to an input being received by said first means; and means responsive to said inputs to be counted for decoupling said clock means from said second means upon receipt of a first of said inputs to be counted.

Claim 3

A counter as defined in claim 1, including: resetting means responsive to the count in said first means for deleting the count of clock pulses in said second means prior to transmittal of carries from said first means to said second means.

Claim 4

A counter for providing a sum of discrete inputs to be counted comprising: first means for counting said inputs to be counted, including carry output means for generating carries when the count in said first means reaches a predetermined level; second means for counting inputs thereto; third means for coupling said carry output means to said second means to enable said second means to count carries generated by said carry output means; clock means for generating clock signals at regular intervals; gate means responsive to inputs to said first means for transmitting said clock signals to said second means during an interval which terminates upon the receipt of an input by said first means; reset means responsive to the count in said first means for resetting the count in said second means to a reference level upon the attainment of a predetermined count in said first means; and means responsive to the operation of said reset means for indicating that the count in said second means represents only carries.

Claim 5

A counter for providing a sum of discrete inputs to be counted comprising: first means for counting said inputs to be counted, including carry output means for generating carries when the count in said first means reaches a predetermined level; second means for counting inputs thereto; third means for coupling said carry output means to said second means to enable said second means to count carries generated by said carry output means; clock means for generating clock signals at regular intervals; gate means responsive to inputs to said first means for transmitting said clock signals to said second means during an interval which terminates upon the receipt of an input by said first means; reset means responsive to the count in said first means for resetting the count in said second means to a reference level upon the attainment of a predetermined count in said first means; and means responsive to the operation of said reset means for indicating that the count in said second means represents only carries.

Claim 6

A counter for providing a sum of discrete inputs to be counted comprising: a first plurality of binary cells connected in tandem to count said inputs, with a first of said binary cells responsive to said inputs to be counted and another of said binary cells constructed to generate carries when the count in said first plurality of cells reaches a predetermined level; a second plurality of binary cells connected in tandem; means for coupling carries from first plurality of cells to said second plurality of cells, to enable said second plurality of cells to count carries; clock means for generating clock signals; gate means for delivering said clock signals to a first cell of said second plurality of cells when said gate means is open; means for closing said gate means when a first input to be counted is received by said first cell of said first means; reset means responsive to the count in said first plurality of cells for setting the count in said second plurality of cells to an initial value between the attainment of a count in said first plurality of cells equal to the highest count registerable therein before a carry is generated and the receipt of one input to be counted after the attainment of said highest count; and output means coupled to said reset means for indicating the occurence of a setting of the count in said second plurality of cells to said initial value.

Claim 7

A counter for providing a sum of discrete inputs to be counted comprising: a first plurality of binary cells connected in tandem to count said inputs, with a first of said binary cells responsive to said inputs to be counted and another of said binary cells constructed to generate carries when the count in said first plurality of cells reaches a predetermined level; a second plurality of binary cells connected in tandem; means for coupling carries from first plurality of cells to said second plurality of cells, to enable said second plurality of cells to count carries; clock means for generating clock signals; gate means for delivering said clock signals to a first cell of said second plurality of cells when said gate means is open; means for closing said gate means when a first input to be counted is received by said first cell of said first means; reset means responsive to the count in said first plurality of cells for setting the count in said second plurality of cells to an initial value between the attainment of a count in said first plurality of cells equal to the highest count registerable therein before a carry is generated and the receipt of one input to be counted after the attainment of said highest count; and output means coupled to said reset means for indicating the occurence of a setting of the count in said second plurality of cells to said initial value.

Claim 8

A counter for counting input pulses during a sampling period comprising: a first plurality of binary memory cells connected in tandem, a first of said cells having an input for receiving said input pulses to be counted and a last of said cells having an output for generating carries; a second plurality of cells connected in tandem for registering counts; first reset means coupled to said first plurality of cells for resetting said first plurality of cells to a state indicating a zero count therein; second reset means coupled to said second plurality of cells for resetting said second plurality of cells to a state indicating a zero count therein; operating means coupled to said first and second reset means to operate them and establish a zero count in said first and second plurality of cells at the beginning of a sampling period; clock means for generating clock signals; a gate responsive to a first input pulse to be counted for passing signals from said clock means to a cell of said second plurality of cells during an interval which terminates upon the receipt of a first pulse to be counted by said first plurality of cells; means responsive to said operating means for opening said gate at the beginning of a sampling period; overflow means responsive to the count in said first plurality of cells and coupled to said seocnd reset means for resetting said second plurality of cells to an initial count at a time substantially between the attainment of a maximum count in said first plurality of cells and the delivery of a carry therefrom; and means coupling a last of said first plurality of cells to a first cell of said second plurality of cells for enabling the counting of carries from said first plurality of cells by said second plurality of cells.

Claim 9

A counter for counting input pulses during a sampling period comprising: a first plurality of binary memory cells connected in tandem, a first of said cells having an input for receiving said input pulses to be counted and a last of said cells having an output for generating carries; a second plurality of cells connected in tandem for registering counts; first reset means coupled to said first plurality of cells for resetting said first plurality of cells to a state indicating a zero count therein; second reset means coupled to said second plurality of cells for resetting said second plurality of cells to a state indicating a zero count therein; operating means coupled to said first and second reset means to operate them and establish a zero count in said first and second plurality of cells at the beginning of a sampling period; clock means for generating clock signals; a gate responsive to a first input pulse to be counted for passing signals from said clock means to a cell of said second plurality of cells during an interval which terminates upon the receipt of a first pulse to be counted by said first plurality of cells; means responsive to said operating means for opening said gate at the beginning of a sampling period; overflow means responsive to the count in said first plurality of cells and coupled to said seocnd reset means for resetting said second plurality of cells to an initial count at a time substantially between the attainment of a maximum count in said first plurality of cells and the delivery of a carry therefrom; and means coupling a last of said first plurality of cells to a first cell of said second plurality of cells for enabling the counting of carries from said first plurality of cells by said second plurality of cells.

Claim 10

A counter as defined in claim 5 wherein: said second reset means comprises an AND gate having inputs connected to an output of each of said cells in said first plurality of cells and an output connected to each of said cells of said second plurality of cells.

Claim 11

A counter as defined in claim 5 including: means coupled to said overflow means for generating a binary signal indicating the occurrence of a resetting of said second plurality of cells substantially between said attainment of a maximum count in said first plurality of cells and the delivery of a carry therefrom.