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US3566207A Expired / Lapsed US ⏱️ 0.0 years remaining

Silicon-to-gold bonded structure and method of making the same

Assignee: Singer Co
•
Filing: 1969-05-19
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Granted: 1971-02-23
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Expires: 1989-05-19
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Abstract

Abstract A silicon chip, constituting the substrate of an integrated circuit, is coated first with chromium, and then tin, to provide a surface that will bond at temperatures as low as 217* C. to a gold-surfaced mounting pad.

Inventors

  • 👤 Clark N Adams

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 12:18
CPC Classifications
B; B23; B23K; B23K35/00; B23K35/001; B23K2035/008; H; H10; H10W; H10W72/00; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336; H10W72/30; H10W72/351; H10W72/352; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 102 words
The method according to claim 1 wherein said temperature is about 217* C. 3. A method of bonding a silicon-surfaced electronic circuit device to a gold-surfaced support member comprising the steps of: vapor-phase depositing a layer of chromium on the silicon surface of said circuit device; vapor-phase depositing a layer of tin on a surface of the layer of chromium; placing a surface of the tin layer against the gold surface of said support member; and raising the temperature of the gold and tin to about 217* C. for forming a gold-tin eutectic alloy, thereby bonding said device to said support member.
Claim 2
Independent Claim 169 words
A method in the making of an integrated circuit device which comprises the steps of: forming a plurality of integrated circuits on one face of a silicon wafer; vapor phase depositing chromium on the opposite face of said wafer; vapor phase depositing tin on the chromium so deposited; separating said wafer into a plurality of chips, each chip having an integrated circuit contained thereon; placing individual ones of said separated chips on individual gold-surfaced mounting pads so that said tin of the chip is in surface contact with the gold surface of the mounting pad; and heating the thus contacted chips and mounting pads to a gold-tin eutectic alloy forming temperature. 5. An electronic device comprising: a substantially flat member of silicon having an obverse surface and a reverse surface; an integrated circuit disposed on said obverse surface; a layer of chromium on said reverse surface; a layer of tin on said layer of chromium; and a gold-surfaced mounting member in eutectic bonded relation with said layer of tin.
Claim 3
Dependent Claim 149 words
An electronic device comprising: a substantially flat member of silicon having an obverse surface and a reverse surface; an integrated circuit disposed on said obverse surface, said integrated circuit including layers of material that operatively degenerate at temperatures above a predetermined temperature; a gold-plated base member; and a layer of bonding material in adhesive contact with said reverse surface of said silicon member and in eutectic bond with the gold plating of said base member; said bonding material being a material which forms said eutectic bond at a temperature less than said predetermined temperature. 7. An electronic device according to claim 6 wherein said layer of bonding material includes a layer of chromium in adhesive contact with said reverse surface of said silicon member, and a layer of tin in eutectic bond relation with said gold plate; said chromium and said tin being in adhesive relation with each other.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-02-22 1974-08-24 1975-02-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-02-22 1978-08-24 1979-02-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-02-22 1982-08-24 1983-02-23 $7700.00 Window Closed / Lapsed

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