US3565227A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Coin counting and registering circuit
Assignee: POLYTECHNIC DATA CORP
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Filing: 1969-03-26
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Granted: 1971-02-23
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Expires: 1989-03-26
Abstract
Abstract A coin counting and registering circuit is disclosed which accumulates inputs representing the insertion or introduction of coins of different denominations to indicate that a selected total has been accumulated.
Inventors
- 👤 Nicholas P Flevaris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:33
CPC Classifications
G; G07; G07F; G07F5/00; G07F5/20; G07F5/22
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
222 words
A coin counting and registering or summing means comprising, in combination, means for receiving coins of various denominations and selectively providing electrical pulses in response thereto, a plurality of bistable means adapted to be set and reset to second and first stable operating states respectively in response to selective electrical pulses to provide binary output voltages and thereby give an indication of the reception of selected coins, network means including a capacitor and resistors for coupling an output voltage from the first bistable means to the second bistable means to set said second bistable means to its second stable state when said first bistable means is reset, said second bistable mans having its output connected to the third bistable means, said third bistable means being set when said second bistable means is reset, first gate means for selectively receiving an output voltage from a first and a third of said bistable means to provide feedback voltages to reset said bistable means, second gate means for selectively receiving output voltages from said second and said third bistable means for providing feedback voltages to said first bistable means and to reset said second and third bistable means, and third gate means for receiving output voltages from said first and seconD gate means to actuate succeeding bistable means to thereby provide an accumulated total indication.
Claim 2
Dependent Claim
222 words
A coin counting and registering or summing means comprising, in combination, means for receiving coins of various denominations and selectively providing electrical pulses in response thereto, a plurality of bistable means adapted to be set and reset to second and first stable operating states respectively in response to selective electrical pulses to provide binary output voltages and thereby give an indication of the reception of selected coins, network means including a capacitor and resistors for coupling an output voltage from the first bistable means to the second bistable means to set said second bistable means to its second stable state when said first bistable means is reset, said second bistable mans having its output connected to the third bistable means, said third bistable means being set when said second bistable means is reset, first gate means for selectively receiving an output voltage from a first and a third of said bistable means to provide feedback voltages to reset said bistable means, second gate means for selectively receiving output voltages from said second and said third bistable means for providing feedback voltages to said first bistable means and to reset said second and third bistable means, and third gate means for receiving output voltages from said first and seconD gate means to actuate succeeding bistable means to thereby provide an accumulated total indication.
Claim 3
Dependent Claim
47 words
A coin counting and summing circuit as in claim 1 wherein said plurality of bistable means comprises three flip-flop units connected to operate in a bistable manner wherein each flip-flop is actuated to indicate a sum of twice the sum indicated by operation of the preceding flip-flop.
Claim 4
Dependent Claim
195 words
A coin counting and summing circuit as in claim 1 further including mechanical switch means actuatable to provide electrical pulses in response to the insertion of a coin in an associated slot, latch means coupled to said switch means and shiftable from a set to a reset operating condition to provide output signals in response to electrical pulses received from said switch means, delay means coupled to receive output signals from said latch means and provide a time delayed pulse in response thereto, means to couple the output pulse from said delay means to reset said latch means to its initial condition, whereby said latch is shifted from a set to a reset condition in response to an electrical pulse received from said switch and remains in said condition until it is reset by a pulse from said delay means such that only one signal effective electrical pulse representative of the actuation of said mechanical switch means is provided in response to the insertion of a coin in the associated slot and any electrical pulses caused by bouncing of said mechanical switch are prevented from effecting the operation of the coin counting and summing circuit.
Claim 5
Dependent Claim
46 words
A coin counting and summing circuit as in claim 3 wherein three mechanical switches are provided each actuable respectively by a 5 cent, 10 cent and 25 cent coin, and wherein a pulse developed by each mechanical switch is directly coupled to a respective bistable means.
Claim 6
Dependent Claim
49 words
A coin counting and summing circuit as in claim 1 wherein said network means comprises a capacitor connected in series between said first and second bistable means, and resistor means connected across a source of potential and having an intermediate point of said resistor means connected to said capacitor.
Claim 7
Dependent Claim
40 words
A coin counting and summing circuit as in claim 1 wherein said gate means each comprise an AND gate and include capacitor means connected to said AND gate to shape and extend the output voltage pulse from said AND gate.
Claim 8
Dependent Claim
24 words
A coin counting an summing circuit as in claim 1 further including an accumulator for accumulating and recording the total sum of said coins.
Claim 9
Dependent Claim
41 words
A coin counting and summing circuit as in claim 7 wherein the output of each of said bistable means are also connected directly to said accumulator to thereby provide an indication of the reception of a coin directly to said accumulator.
Claim 10
Dependent Claim
32 words
A coin counting and summing circuit as in claim 1 further including a plurality of bistable means each connected to indicate a sum of twice that indicated by the preceding bistable means.
Claim 11
Dependent Claim
22 words
A coin counting and summing circuit as in claim 1 wherein means are provided to reset all of said bistable means concurrently.
References Cited (Backward Citations)
US3431920A
Cited
US3323527A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-22 | 1974-08-24 | 1975-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-22 | 1978-08-24 | 1979-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-22 | 1982-08-24 | 1983-02-23 | $7700.00 | Window Closed / Lapsed |