Electrical sampling arrangement

Claim 3

An apparatus as claimed in claim 1, in which said memory device includes an amplifier, means to gate said amplifier on, a feedback capacitor connected to said amplifier in such a manner that the current fed to said capacitor is directly proportional to the amplitude of the input voltage during the time that said amplifier is gated on and an input circuit which provides a virtual earth point and has a low input impedance.

Claim 4

An apparatus as claimed in claim 1, in which said feedback loop further includes a virtual earth amplifier comprising a first transistor connected in common base configuration, a second transistor connected in common emitter configuration, emitter, collector and base electrodes to said first and second transistors, a signal input connected to the emitter electrode of said first transistor, the collector electrode of said first transistor connected to the base electrode of said second transistor, a resistive element connected as a feedback resistance between the collector electrode of said second transistor and the emitter electrode of said first transistor, and a constant current generator connected to each of the collector and emitter electrodes of said first transistor.

Claim 5

An apparatus as claimed in claim 1, in which said memory device comprises first, second and third transistors of one conductivity type and fourth and fifth transistors of opposite conductivity type to said one conductivity type, base, emitter and collector electrodes to each of said transistors, and in which said first and second transistors are connected to form a differential amplifier wIth their emitter electrodes interconnected, a terminal is provided in the collector circuit of the first transistor for connection to a first source of gating pulses, a first signal input terminal is connected to said first transistor base, a capacitor is connected to said second transistor base, a first output terminal is connected to said capacitor, a feedback resistive element is connected between said second transistor base and an electrical connection extending between a second signal input terminal and a second output terminal, a further resistive element is connected between said electrical connection and said first transistor base, the collector electrodes of said third and fourth transistors are connected to said first output terminal, a further terminal is provided for connection to a second source of gating pulses and which is connected to the base of said third transistor, the collector electrode of said fifth transistor is connected to said electrical connection, the base electrode of said fifth transistor is connected to the collector electrode of said fifth transistor and the emitter electrode of said fifth transistor is connected to the base electrode of said fourth transistor.

Claim 6

An apparatus as claimed in claim 1, in which the memory device is a capacitor connected to the output circuit of an amplifier.

Claim 7

An apparatus as claimed in claim 5, in which the amplifier circuit including the capacitor is a differential amplifier circuit and in which there is a feedback path for the stored signal to an input to the differential amplifier, means being provided to prevent the discharge of the capacitor during normal operation, whereby the charge on the capacitor is varied according to the difference between the values of the samples as a function of the change in value of the pulses sampled.

Claim 8

An apparatus as claimed in claim 1, in which said control means to open the sampling gate at successive instants includes a time base having a slow ramp sawtooth waveform generator, a fast ramp sawtooth waveform generator and a comparator, the outputs from the generators being applied to the comparator, whereby output pulses are obtained from the comparator at the instants when the fast ramp signal intersects the slow ramp signal.

Claim 9

An apparatus as claimed in claim 7, further comprising a sawtooth waveform generator in the time base circuit having a capacitor and a pair of transistors connected to form a bistable circuit and which is arranged to discharge said capacitor and to be triggered in accordance with a synchronizing pulse.

Claim 10

An apparatus as claimed in claim 7, further comprising a sawtooth waveform generator in the time base circuit, said sawtooth waveform generator including first and fourth transistors of one conductivity type and second, third and fifth transistors of opposite conductivity type to said one conductivity type, base, collector and emitter electrodes to each of said transistors, a capacitor, a constant current generator connected to charge said capacitor, and in which said first and second transistors are connected to form a bistable pair with the collector electrode of the second transistor connected to base electrode of the first transistor, the collector electrode of the first transistor connected to the base electrode of the second transistor; a terminal for connection to a synchronizing pulse source is connected to the base electrode of the second transistor, a diode is connected between the emitter electrode of said second transistor and one side of said capacitor; said third transistor is connected in emitter follower configuration with its base electrode connected to said one side of the capacitor and an output terminal connected to its emitter electrode; and said fourth and fifth transistors constituting a feedback loop with the emitter electrode of said fourth transistor connected to said output terminal, the base electrode of said fourth transistor connected to a tap of a potential divider, the collector electrode of said fourth tRansistor connected to the base electrode of said fifth transistor and the collector electrode of said fifth transistor connected to the base electrode of said second transistor.

Claim 11

An apparatus as claimed in claim 7 having a tunnel diode stage in the time base circuit connected to provide a regular ''''holding off'''' of the signals applied to it.