Serial binary coded decimal converter

Claim 2

A binary to decimal converter for converting between a number expressed in binary notation and a number expressed in binary coded decimal notation, comprising: a shift register having a recirculation path and a predetermined number of bit positions to receive the bits of the number to be converted; means for recirculating said register by shifting the bits of said register in the direction of decreasing significance by a number of bit positions equal to the number of bit positions in said recirculation path plus or minus one during each recirculating cycle to produce during each recirculating cycle partially converted numbers having a plurality of decades; means for generating an output signal each time one of said decades in the four least significant bit positions of said shift register is greater than four, or seven; means for generating a binary signal representing the value of three in response to said output signal; and a serial binary full adder-subtracter in said recirculation path for adding and subtracting said binary signal representing the value of three to said partially converted numbers.

Claim 3

A binary to decimal converter for converting a number expressed in binary notation to said number expressed in binary coded decimal notation, comprising: a shift register having a recirculation path and a predetermined number of bit positions to receive the bits of said number in binary notation; means for recirculating said register by shifting the bits of said register in the direction of decreasing significance by a number of bit positions equal to the number of bit positions in said recirculation path minus one during each recirculating cycle to produce during each recirculating cycle partially converted binary coded decimal numbers having a plurality of decades, means for generating an output signal each time one of said decades of said partially converted binary-coded decimal numbers in the four least significant bit positions of said shift register is greater than four; means responsive to said output signal for generating a binary signal representing the value of three; and a serial binary full adder-subtracter for adding said binary signal representing the value of three to said one of said decades in said recirculating cycle.

Claim 4

A binary to decimal converter for converting a number expressed in binary notation to said number expressed in binary coded decimal notation, comprising: a shift register having a recirculation path and a predetermined number of bit positions to receive the bits of said number in binary notation; means for recirculating said register by shifting the bits of said register in the direction of decreasing significance by a number of bit positions equal to the number of bit positions in said recirculation path minus one during each recirculating cycle to produce during each recirculating cycle partially converted binary coded decimal numbers having a plurality of decades, means for generating an output signal each time one of said decades of said partially converted binary-coded decimal numbers in the four least significant bit positions of said shift register is greater than four; means responsive to said output signal for generating a binary signal representing the value of three; and a serial binary full adder-subtracter for adding said binary signal representing the value of three to said one of said decades in said recirculating cycle.

Claim 5

The apparatus recited in claim 2 further including a second shift register having a recirculation path and a predetermined number of bit positions for receiving said number expressed in binary notation, said least significant bit position of said second shift register being connected to insert one bit of a said number expressed in binary notation into the least significant bit position Of said first shift register during each recirculating cycle.

Claim 6

The apparatus recited in claim 2 wherein the means for generating an output signal includes: a first gate having an input connected to sense the 1 state of the fourth from the least significant bit position of said shift register; a second gate having an input connected to sense the 1 state of the third from the least significant list position and either of the least significant or second from least significant bit positions of said shift register; and an OR circuit, the outputs of said first and second gates being applied to said OR circuit, the output of said OR circuit producing said output signal.

Claim 7

The apparatus recited in claim 2 wherein said means responsive to said output signal is a flip-flop, said flip-flop being set at a 1 condition by said output signal, said flip-flop being reset by a clock pulse occurring two bit times after the occurrence of said output signal.