Digital differential analyzer

Claim 2

A digital differential analyzer for calculating a specified function of an independent variable, comprising: input means for providing a digital representation of a sample value of the independent variable and a digital representation of an increment therein; first storage means for temporarily storing a digital representation of a previously calculated value of the function; computing means connected to the input means and to the first storage means for forming a digital representation of the sum of the first n terms of a Taylor series expansion of the function with the substitution therein of the said increment and the said previously calculated value, thereby forming a new representation of an approximation to the value of the function corresponding to the sampled value of the variable; and means for replacing the aforesaid representation of the previously calculated value stored in the first storage means by the said new representation formed by the computing means wherein n is an odd integer greater than unity.

Claim 3

A digital differential analyzer for calculating a function of a variable, comprising: first storage means for temporarily storing a digital representation of a previously calculated value of the function; second storage means for temporarily storing a representation of a value of the independent variable associated with a preceding calculation; sample input means for providing a representation of a sample value of the variable; increment-detecting means connected to the sample input means and to the second storage means, for comparing the representation stored in the second storage means with the representation provided by the sample input means, providing an increment sign signal indicative of the sign of the difference between the said sample value and the said value associated with a preceding calculation and providing an increment size signal indicative of whichever one of two predetermined standard increment sizes has a magnitude nearer to the magnitude of the said difference, and computing means, connected to the first storage means and to the increment-detecting means and responsive to the increment sign signal and to the increment size signal, for forming a digital representative of the sum of the first n terms of a Taylor series expansion of the function with the substitution therein of an increment in the value of the variable having the sign indicated by the increment sign signal and a magnitude equal to the magnitude of the said one of the two predetermined standard increment sizes, and also for altering the representations in the first storage means and the second storage means to represent the effect of the said increment on the value of the variable.

Claim 4

A digital differential analyzer for calculating a function of a variable, comprising: first storage means for temporarily storing a digital representation of a previously calculated value of the function; second storage means for temporarily storing a representation of a value of the independent variable associated with a preceding calculation; sample input means for providing a representation of a sample value of the variable; increment-detecting means connected to the sample input means and to the second storage means, for comparing the representation stored in the second storage means with the representation provided by the sample input means, providing an increment sign signal indicative of the sign of the difference between the said sample value and the said value associated with a preceding calculation and providing an increment size signal indicative of whichever one of two predetermined standard increment sizes has a magnitude nearer to the magnitude of the said difference, and computing means, connected to the first storage means and to the increment-detecting means and responsive to the increment sign signal and to the increment size signal, for forming a digital representative of the sum of the first n terms of a Taylor series expansion of the function with the substitution therein of an increment in the value of the variable having the sign indicated by the increment sign signal and a magnitude equal to the magnitude of the said one of the two predetermined standard increment sizes, and also for altering the representations in the first storage means and the second storage means to represent the effect of the said increment on the value of the variable.

Claim 5

A digital differential analyzer as claimed in claim 2 and wherein the first storage means includes a first shift register, the computing means is connected to the first shift register to receive signAls sequentially through an output thereof for making a serial digit-by-digit calculation of the new value of the function, and there is provided a timing signal means connected to a shift control input of the first shift register, to the input means and to the computing means for synchronizing the operations thereof.

Claim 6

A digital differential analyzer as claimed in claim 2 and wherein: the second storage means comprises a second shift register; the sample input means comprises a third shift register; there is provided a timing signal means connected to shift control inputs of the second shift register and the third shift register; and the increment detecting means is connected to one output connection of the second shift register and one output connection of the third shift register for making a serial digit-by-digit comparison of digital representations stored therein.

Claim 7

A digital differential analyzer as claimed in claim 4 and wherein the increment-detecting means comprises a subtractor circuit means connected to the said output connection of the second shift register and the said output connection of the third shift register and to the timing signal means for successively forming difference signals representing digits of the said difference, and a plurality of gate circuits connected to the subtractor circuit means and connected to the timing signal means and controlled thereby to provide a fine-increment-indicating signal whenever the magnitude of the said difference is greater than a first predetermined magnitude and to provide a coarse-increment-indicating signal whenever the said difference is greater than a second predetermined magnitude.

Claim 8

A digital differential analyzer as claimed in claim 3 and wherein the first shift register has an output connection connected from an intermediate stage of the first shift register and to the computing means to provide it with signals representing the product of a stored value multiplied by a predetermined multiplier.

Claim 9

A digital differential analyzer as claimed in claim 6, wherein the digital representations of the increments and the values of the function comprise ordered sets of binary digit-signals, of which a first digit-signal is a sign-indicating signal which is a zero signal in representations of positive values and is a 1-signal in representations of negative values; of which a second digit-signal may be a 0-signal of unit significance representing zero units or a 1-signal which represents minus unity in representations of negative values; a third digit signal of half-unit significance which will represent plus one-half unit in all representations where it is a 1-signal and a plurality of binary digit-signals of consecutively decreasing significance which represent positive binary fractional quantities in all representations; and wherein the computing means comprises a sign digit repeater means connected to the timing signal means for causing repetitions of the sign indicating signal in any subtrahend formed by a shift in the direction of decreasing significance.

Claim 10

A digital differential analyzer as claimed in claim 6, wherein the first shift register has a first output connection and a second output connection connected to different intermediate stages of the first shift register, the computing means comprises a first gate connected to the said first output connection and a second gate connected to the said second output connection, and the said first gate and the said second gate are both connected to the increment detecting means so as to be opened by different increment size signals provided by the increment detecting means.

Claim 11

A digital differential analyzer as claimed in claim 3 and wherein the computing means comprises an adder/subtractor circuit and a plurality of gate circuits connected to the adder/subtractor circuit and to the timing signal means.

Claim 12

A digital differential analyzer as claimed in claim 9 and wherein the computing means comprises a sequence control means coNnected to the timing signal means and connected to the increment-detecting means to receive the increment sign signal therefrom, for controlling the adder/subtractor circuit so that it performs additions and subtractions in a first predetermined sequence whenever the increment sign signal indicates the occurrence of a positive increment and in a second predetermined sequence whenever the increment sign signal indicates the occurrence of a negative increment.

Claim 13

A digital differential analyzer as claimed in claim 2 for calculating sine and cosine functions of an angle which in this case is the independent variable, wherein the said first storage means comprises a shift register for temporarily storing a digital representation of a previously calculated value of the sine of a value of the angle, and the computing means comprises: another shift register for temporarily storing a digital representation of a previously calculated value of the cosine of a value of the angle; a further shift register for temporarily storing digital representations formed in the course of the calculations; a timing signal means having a plurality of outputs for producing a sequence of timing signals, of which at least one output is connected to shift control inputs of the said shift registers; a plurality of gate circuits connected to outputs of the timing signal means, to the said shift registers and to the increment detector means; an adder/subtractor circuit connected to outputs of the said gate circuits and having an output connected through some of the aforesaid gate circuits to inputs of the said shift registers, and a sequence control means which has inputs connected to the timing signal means, at least one input connected to the increment detecting means to receive the increment sign signal therefrom, and at least one output connected to the adder/subtractor circuit for causing it to perform additions and subtractions in a first predetermined sequence whenever the increment sign signal indicates the occurrence of a positive increment and in a second predetermined sequence whenever the increment sign signal indicates the occurrence of a negative increment.

Claim 14

A digital differential analyzer as claimed in claim 11 and comprising resetting means for resetting the first shift register, the second shift register, and the said another shift register to representations of zero, zero and unity respectively.

Claim 15

A digital differential analyzer as claimed in claim 11 wherein the said plurality of gate circuits comprises: a first gate circuit connected in a signal path from the last stage to the first stage of the said first shift register; a second gate circuit connected in a signal path from the last stage of the first shift register to an input of the adder/subtractor circuit; a third gate circuit connected in a signal path from the last stage to the first stage of the said another shift register; a fourth gate circuit connected in a signal path from the last stage of the said another shift register to an input of the adder/subtractor circuit; a fifth gate circuit connected in a signal path from an output of the adder/subtractor circuit to the first stage of the first shift register; a sixth gate circuit connected in a signal path from the output of the adder/subtractor circuit to the first stage of the said further shift register; a seventh gate circuit connected in a signal path from the output of the adder/subtractor circuit to the first stage of the said another shift register; an eighth gate circuit having two inputs connected to different stages of the first shift register; a ninth gate circuit having two inputs connected to different stages of the said further shift register; a 10th gate circuit having two inputs connected to different stages of the said another shift register; wherein outputs of the eighth, ninth and 10th gate circuits have outputs connected to an input of the adder/sUbtractor circuit, and have inputs connected to the increment detector means to receive increment size signals therefrom; and wherein the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth and 10th gate circuits all have inputs connected to various outputs of the timing signal means.

Claim 16

A digital differential analyzer as claimed in claim 13 and comprising a sign digit repeater circuit connected in the signal path from the outputs of the eighth, ninth and 10th gate circuits to the adder/subtractor circuit, connected to the timing signal means and connected to the increment detecting means to receive at least one increment size signal therefrom.

Claim 17

A digital differential analyzer as claimed in claim 13 and wherein each of the eighth, ninth and 10th gate circuits comprises: a first AND-gate having an input connected to an intermediate stage of a shift register and an input connected to the increment detecting means so that it will transmit signals from the said intermediate stage when an increment size signal indicative of a fine increment is produced; a second AND-gate having an input connected to a stage of the shift register later than the said intermediate stage and an input connected to the increment detecting means so that it will transmit signals from the later stage when an increment size signal indicative of a coarse increment is produced; and a third AND-gate connected to receive signals from the output of the first AND-gate, the output of the second AND-gate, and at least one output of the timing signal means.