Bidirectional counting system

Claim 1

In a bidirectional counting system for a position indicating device wherein the displacement of a movable component is monitored by an interferometer, the combination comprising: a. an interferometer feedback generator for sensing movement of said component and generating first and second phase-displaced signals for each increment of movement of said component sensed by said feedback generator, said first signal leading said second signal when a forward movement is sensed and said second signal leading said first signal when a reverse movement is sensed; b. a phase detector connected to receive said first and second signals from said feedback generator and producing a ''''forward'''' count pulse at a forward output when said first signal is leading and producing a ''''reverse'''' count pulse at a reverse output when said second signal is leading; c. a bidirectional counter including a first input terminal for receiving ''''forward'''' count pulses connected to said forward count output of said phase detector; d. a second input terminal for receiving ''''reverse'''' count pulses connected to said reverse count output of said phase detector; e. a plurality of binary stages divided into 10N binary counting decades, each of said decades including four binary stages, each of said binary stages having a flip-flop operable in either a ''''set'''' or ''''reset'''' state, said flip-flop having a set and reset input and corresponding outputs, and first and second OR gates connected respectively to said set and reset inputs of said flip-flop, each of said OR gates having a first input connected to receive pulses representing an increase in the count and a second input connected to receive pulses representing a decrease in the count, said first input terminal of said counter connected to said first inputs of said OR gates of a first binary stage, and said second input terminal of said counter connected to said second inputs of said OR gates of said first binary stage; f. a plurality of forward count AND gates each having an output connected to respective first inputs of said first and second OR gates of each of said stages, excluding said first stage, each of said forward AND gates having a first input for receiving forward count pulses and further inputs connected to said set outputs, respectively, of each preceding stage so that the existing state of said flip-flop of each of said stages enables the counter to receive and register according to a predetermined binary counting order said forward count pulses applied to said first input terminal of said counter; g. a plurality of reverse count AND gates, each having an output connected to respective second inputs of said first and second OR gates of each of said stages, excluding said first stage, each of said revErse count AND gates having a first input connected to said second input terminal of said counter and further inputs connected to said ''''reset'''' outputs of the flipflops of each preceding stage so that the existing state of said flip-flops of each of said stages enables the counter to receive and register according to said predetermined binary counting order said ''''reverse'''' pulses applied to said second input terminal of said counter; h. a forward pulse carry AND gate having an output connected to the forward count input of a next succeeding decade, said forward pulse carry AND gate having a first input connected to receive even numbered forward count pulses and a second input connected to said set output of the fourth binary stage of said decade, said AND gate connected to said second input of said first OR gate of said third stage of said decade having a further input connected to said set output of said fourth stage, said AND gate connected to said first input of said first OR gate of said second stage of said decade having a further input connected to said reset output of said fourth stage of said decade; i. a further AND gate having first, second and third inputs connected to said reset outputs of said flip-flops of said second, third and fourth stages, respectively; j. an inverter connected between the output of said further AND gate and a third input of said reverse count AND gate connected to said second input of said first OR gate of said second stage; and k. a reverse pulse carry AND gate having an output connected to the reverse input of said next succeeding decade, said reverse carry AND gate having a first input connected to said second input terminal of said counter, a second input connected to said reset output of said first stage, and a third input connected to the output of said further AND gate.