US3562433A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital speech plus telegraph system
Assignee: United States Department of the Army
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Filing: 1968-06-27
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Granted: 1971-02-09
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Expires: 1988-06-27
Abstract
Abstract A multiplex communication system for interleaving vocoder, telegraphic, and control digital signals into a single channel. A predetermined number of vocoder digits are stored in a shift register at a relatively high bit rate. These bits are then transferred in parallel to a second shift register via a series of AND gates which are gated on at a relatively low bit rate. The telegraphic and control signals are alternately inserted into the second shift register at the relatively low bit rate. The second shift register is then shifted at a rate which is the sum of the high bit rate and the low bit rate. A transmission line is connected to the output of the second shift register for transmitting the multiplexed information The invention described herein may be manufactured, used, and licensed by or for the Government for governmental purposes without the payment to me of any royalty thereon.
Inventors
- 👤 Mario Ambrosio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:23
CPC Classifications
H; H04; H04M; H04M11/00; H04M11/06; H04M11/064; H04J; H04J3/00; H04J3/02; H04J3/12; H04J3/125
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
352 words
A digital multiplexed communication system comprising first and second binary signal sources; clock means for driving said first binary signal sources at a relatively high output bit rate and for driving said second source at a relatively low output bit rate; a first storage means connected to said clock means and to the output of said first signal source for storing in sequence a predetermined number of said binary bits at said high bit rate; transfer means connected to said first storage means and said clock means for transferring in parallel all said binary bits out of said fist storage means; a second storage means, said transfer means and the output of said second signal source connected in parallel to said second storage means for inserting in parallel binary bits therein at said low bit rate; said clock means connected to said second storage means for serially transmitting information out of said second storage means onto a transmission line at a rate which is the sum of said low bit rate and said high bit rate; said first storage means including a shift register; the output of said first signal source connected to one end of said shift register; said clock means including shift means connected to said shift register to shift said register at said high bit rate; said second storage means including a shift register having a greater number of stages then the shift register of said first storage means; said transfer means including a plurality of AND gates equal in number to the number of stages in the shift register of said first storage means; each said register stage of said first storage means being connected by one of said AND gates to different register stages of said second storage means; and said clock means including output means connected to each said AND gate for simultaneously opening said gates at said low bit rate and further including shift means connected to the register of said second storage means for shifting said register at a rate which is the sum of said low bit rate and said high bit rate.
Claim 2
Dependent Claim
352 words
A digital multiplexed communication system comprising first and second binary signal sources; clock means for driving said first binary signal sources at a relatively high output bit rate and for driving said second source at a relatively low output bit rate; a first storage means connected to said clock means and to the output of said first signal source for storing in sequence a predetermined number of said binary bits at said high bit rate; transfer means connected to said first storage means and said clock means for transferring in parallel all said binary bits out of said fist storage means; a second storage means, said transfer means and the output of said second signal source connected in parallel to said second storage means for inserting in parallel binary bits therein at said low bit rate; said clock means connected to said second storage means for serially transmitting information out of said second storage means onto a transmission line at a rate which is the sum of said low bit rate and said high bit rate; said first storage means including a shift register; the output of said first signal source connected to one end of said shift register; said clock means including shift means connected to said shift register to shift said register at said high bit rate; said second storage means including a shift register having a greater number of stages then the shift register of said first storage means; said transfer means including a plurality of AND gates equal in number to the number of stages in the shift register of said first storage means; each said register stage of said first storage means being connected by one of said AND gates to different register stages of said second storage means; and said clock means including output means connected to each said AND gate for simultaneously opening said gates at said low bit rate and further including shift means connected to the register of said second storage means for shifting said register at a rate which is the sum of said low bit rate and said high bit rate.
Claim 3
Dependent Claim
275 words
A digital multiplexed communications system for interleaving digital vocoder signals and digital telegraphic signals comprising a timing means including means for generating clock pulses at a transmission bit rate and at a vocoder bit rate being less then said transmission bit rate; vocoder means connected to said means for generating clock pulses at said vocoder bit rate; first shift register means connected to the output of said vocoder means for storing a predetermined number of said vocoder bits; said means for generating clock pulses at said vocoder bit rate being connected to said first shift register means for shifting said first register means; a second shift register means having a greater number of stages then said first shift register means; transfer means including a plurality of AND gates each connected between different stages of said first register means and different stages of said second register means for simultaneously transferring in parallel the bits in said first register means to said second register means; gating means connected to said means for generating clock pulses for producing gating pulses of a rate which is the difference between said transmission bit rate and said vocoder bit rate; said gating means being connected to each said AND gates for gating open said AND gates; telegraph means connected to one of the stages of said second register means; means controlled by said gating means for inserting telegraphic bits into said second register; means connecting said means for generating clock pulses at said transmission rate to said second register for shifting said register at said transmission rate; and a transmission means connected to the output of said second shift register means.
Claim 4
Dependent Claim
275 words
A digital multiplexed communications system for interleaving digital vocoder signals and digital telegraphic signals comprising a timing means including means for generating clock pulses at a transmission bit rate and at a vocoder bit rate being less then said transmission bit rate; vocoder means connected to said means for generating clock pulses at said vocoder bit rate; first shift register means connected to the output of said vocoder means for storing a predetermined number of said vocoder bits; said means for generating clock pulses at said vocoder bit rate being connected to said first shift register means for shifting said first register means; a second shift register means having a greater number of stages then said first shift register means; transfer means including a plurality of AND gates each connected between different stages of said first register means and different stages of said second register means for simultaneously transferring in parallel the bits in said first register means to said second register means; gating means connected to said means for generating clock pulses for producing gating pulses of a rate which is the difference between said transmission bit rate and said vocoder bit rate; said gating means being connected to each said AND gates for gating open said AND gates; telegraph means connected to one of the stages of said second register means; means controlled by said gating means for inserting telegraphic bits into said second register; means connecting said means for generating clock pulses at said transmission rate to said second register for shifting said register at said transmission rate; and a transmission means connected to the output of said second shift register means.
Claim 5
Dependent Claim
34 words
The device according to claim 2 and further including control means for generating control bits; and means controlled by said gating means for alternately inserting control bits and telegraphic bits into said second register.
References Cited (Backward Citations)
US3387086A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-08 | 1974-08-10 | 1975-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-08 | 1978-08-10 | 1979-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-08 | 1982-08-10 | 1983-02-09 | $7700.00 | Window Closed / Lapsed |