US3558983A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controls for high-current solid-state switches
Assignee: General Electric Co
•
Filing: 1968-06-20
•
Granted: 1971-01-26
•
Expires: 1988-06-20
Abstract
Abstract A solid-state AC switch (comprising inverse parallel thyristors) that ''''opens'''' in high-speed response to abnormally high currents is so controlled as to prevent automatic reclosing if (1) the overcurrent condition persists for longer than a predetermined length of time or (2) an appropriate opening command is received. For relatively high-current applications, inverse parallel sets of plural thyristors are used, and concurrent turn on of the thyristors of each set is promoted by jointly applying thereto composite firing signals comprising a component of relatively short duration and high magnitude superimposed on another component of long duration and relatively low magnitude. D R A W I N G
Inventors
- 👤 Floyd L Steen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:32
CPC Classifications
H; H02; H02H; H02H3/00; H02H3/02; H02H3/021; H02H3/08
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
227 words
In combination: a. a main circuit comprising solid-state controlled switching means which is normally maintained in a relatively low resistance state whereby electric current can easily traverse said main circuit; b. said main circuit being shunted by the combination of another switching means in series with current limiting impedance means; c. first means for serially connecting said main circuit in a load current conducting path between a source of electric power and an electric power load circuit; d. second means operative in immediate response to a condition of abnormally high current in said path for causing said controlled switching means to change from its low resistance, turned on state to a high resistance, turned-off state, whereupon current is forced to traverse said impedance means; e. third means operative in delayed response to said abnormally high current condition for causing said other switching means to turn off, thereby interrupting current through said impedance means, unless said abnormal condition has earlier terminated, said second means being arranged automatically to return said controlled switching means to its low resistance state in response to the termination of said abnormal condition before operation of said third means; f. latching means responsive to operation of said third means for preventing said second means from returning said controlled switching means to its low resistance state; and g. means for subsequently releasing said latching means.
Claim 2
Dependent Claim
227 words
In combination: a. a main circuit comprising solid-state controlled switching means which is normally maintained in a relatively low resistance state whereby electric current can easily traverse said main circuit; b. said main circuit being shunted by the combination of another switching means in series with current limiting impedance means; c. first means for serially connecting said main circuit in a load current conducting path between a source of electric power and an electric power load circuit; d. second means operative in immediate response to a condition of abnormally high current in said path for causing said controlled switching means to change from its low resistance, turned on state to a high resistance, turned-off state, whereupon current is forced to traverse said impedance means; e. third means operative in delayed response to said abnormally high current condition for causing said other switching means to turn off, thereby interrupting current through said impedance means, unless said abnormal condition has earlier terminated, said second means being arranged automatically to return said controlled switching means to its low resistance state in response to the termination of said abnormal condition before operation of said third means; f. latching means responsive to operation of said third means for preventing said second means from returning said controlled switching means to its low resistance state; and g. means for subsequently releasing said latching means.
Claim 3
Dependent Claim
172 words
In combination: a. a main circuit comprising solid-state controlled switching means which is normally maintained in a relatively low resistance, turned-on state whereby electric current can easily traverse said main circuit; b. said main circuit being shunted by the combination of another switching means in series with current limiting impedance means; c. means for serially connecting said main circuit in a load current conducting path between a source of electric power and an electric power load circuit; d. means operative in response to a first command for causing said controlled switching means to change from its turned-on state to a high resistance, turned-off state, whereupon current is forced to traverse said impedance means; e. means operative in response to a second command issued after said first command for causing said other switching means to turn off, thereby interrupting current through said impedance means; f. latching means responsive to said second command for preventing said controlled switching means from resuming its turned on state; and g. means for subsequently releasing said latching means.
Claim 4
Dependent Claim
172 words
In combination: a. a main circuit comprising solid-state controlled switching means which is normally maintained in a relatively low resistance, turned-on state whereby electric current can easily traverse said main circuit; b. said main circuit being shunted by the combination of another switching means in series with current limiting impedance means; c. means for serially connecting said main circuit in a load current conducting path between a source of electric power and an electric power load circuit; d. means operative in response to a first command for causing said controlled switching means to change from its turned-on state to a high resistance, turned-off state, whereupon current is forced to traverse said impedance means; e. means operative in response to a second command issued after said first command for causing said other switching means to turn off, thereby interrupting current through said impedance means; f. latching means responsive to said second command for preventing said controlled switching means from resuming its turned on state; and g. means for subsequently releasing said latching means.
Claim 5
Dependent Claim
52 words
The combination of claim 2 in which said other switching means comprises additional solid-state controlled switching means, and in which a normally closed electromechanical switch is connected in said load current conducting path in series with said main circuit, said electromechanical switch being arranged to open in response to said second command.
Claim 6
Dependent Claim
179 words
In combination: a. a main circuit comprising first solid-state controlled switching means; b. normally enabled first control means for triggering said first switching means which consequently can assume a relatively low resistance, turned-on state whereby electric current can easily traverse said main circuit, said first control means being disabled in response to either a first command or a second command; c. said main circuit being shunted by the combination of second solid-state controlled switching means in series with current-limiting impedance means; d. normally inactive second control means operative when activated for triggering said second switching means which consequently can assume a relatively low resistance, turned-on state, thereby effectively connecting said impedance means in parallel with said main circuit, said second control means being activated in response to said first command; e. means for serially connecting said main circuit in a load current conducting path between a source of electric power and an electric power load circuit; and f. latching means responsive to said second command for maintaining said first control means disabled until said latching means is subsequently released.
Claim 7
Dependent Claim
179 words
In combination: a. a main circuit comprising first solid-state controlled switching means; b. normally enabled first control means for triggering said first switching means which consequently can assume a relatively low resistance, turned-on state whereby electric current can easily traverse said main circuit, said first control means being disabled in response to either a first command or a second command; c. said main circuit being shunted by the combination of second solid-state controlled switching means in series with current-limiting impedance means; d. normally inactive second control means operative when activated for triggering said second switching means which consequently can assume a relatively low resistance, turned-on state, thereby effectively connecting said impedance means in parallel with said main circuit, said second control means being activated in response to said first command; e. means for serially connecting said main circuit in a load current conducting path between a source of electric power and an electric power load circuit; and f. latching means responsive to said second command for maintaining said first control means disabled until said latching means is subsequently released.
Claim 8
Dependent Claim
40 words
The combination set forth in claim 4 including commutating means operative in response to said first command for quenching current in said first switching means which will consequently change abruptly from its turned-on state to a high resistance, turned-off state.
Claim 9
Dependent Claim
39 words
The combination set forth in claim 5 in which said commutating means is also operative in response to said second command, and means is provided for preventing activation of said second control means in response to said second command.
Claim 10
Dependent Claim
184 words
Electric current limiting protective means comprising: a. a main circuit comprising at least first and second thyristors disposed in inverse parallel relationship with one another, and a pair of inductors respectively connected in series with said first and second thyristors; b. said main circuit being shunted by the combination of bidirectionally conductive solid-state controlled switching means in series with current-limiting impedance means; c. means for serially connecting said main circuit in an alternating current conducting path bEtween a source of AC electric power and an AC load circuit; d. normally enabled firing signal generating means for maintaining both of said thyristors continuously turned on; e. first and second commutating means respectively connected to said thyristors and operative when triggered to quench any current then flowing in the associated thyristor, said first and second commutating means being decoupled by said inductors; and f. means responsive to a condition of abnormally high current in said path for substantially simultaneously triggering both of said commutating means and disabling said firing signal generating means, whereupon said thyristors turn off and current is forced to traverse said impedance means.
Claim 11
Dependent Claim
184 words
Electric current limiting protective means comprising: a. a main circuit comprising at least first and second thyristors disposed in inverse parallel relationship with one another, and a pair of inductors respectively connected in series with said first and second thyristors; b. said main circuit being shunted by the combination of bidirectionally conductive solid-state controlled switching means in series with current-limiting impedance means; c. means for serially connecting said main circuit in an alternating current conducting path bEtween a source of AC electric power and an AC load circuit; d. normally enabled firing signal generating means for maintaining both of said thyristors continuously turned on; e. first and second commutating means respectively connected to said thyristors and operative when triggered to quench any current then flowing in the associated thyristor, said first and second commutating means being decoupled by said inductors; and f. means responsive to a condition of abnormally high current in said path for substantially simultaneously triggering both of said commutating means and disabling said firing signal generating means, whereupon said thyristors turn off and current is forced to traverse said impedance means.
Claim 12
Dependent Claim
156 words
Electric current switching means comprising: a. a first set of at least two parallel, unidirectionally conducting thyristors; b. a second set of at least two parallel, unidirectionally conducting thyristors; c. means for connecting said first and second sets of thyristors in inverse parallel relationship with one another in a circuit adapted to conduct alternating current; d. control means operative when enabled for maintaining all of said thyristors turned on comprising: i. first means for generating a first firing signal of long duration and relatively low magnitude; ii. second means for generating a train of second firing signals each having relatively short duration and high magnitude; iii. means for synchronizing the second firing signals with zero crossings of the alternating current in said circuit; and iv. coupling means for jointly applying said first and second firing signals to each of the thyristors in said first set; and e. means for selectively enabling and disabling said control means.
Claim 13
Dependent Claim
156 words
Electric current switching means comprising: a. a first set of at least two parallel, unidirectionally conducting thyristors; b. a second set of at least two parallel, unidirectionally conducting thyristors; c. means for connecting said first and second sets of thyristors in inverse parallel relationship with one another in a circuit adapted to conduct alternating current; d. control means operative when enabled for maintaining all of said thyristors turned on comprising: i. first means for generating a first firing signal of long duration and relatively low magnitude; ii. second means for generating a train of second firing signals each having relatively short duration and high magnitude; iii. means for synchronizing the second firing signals with zero crossings of the alternating current in said circuit; and iv. coupling means for jointly applying said first and second firing signals to each of the thyristors in said first set; and e. means for selectively enabling and disabling said control means.
Claim 14
Dependent Claim
90 words
The switching means of claim 8 in which said first means is arranged simultaneously to generate first firing signals for the respective sets of thyristors, said second means is arranged simultaneously to generate trains of second firing signals for the respective sets of thyristors, and said coupling means is arranged to jointly apply the first and second firing signals for said second set to each of the thyristors in that set at the same time it jointly applies first and second firing signals to each thyristor in said first set.
Claim 15
Dependent Claim
39 words
The switching means of claim 8 in which said second means is arranged to generate an initial second firing signal at the moment of time when said control means is changed from a disabled state to an enabled state.
Claim 16
Dependent Claim
38 words
The switching means of claim 10 in which the paralleled sets of thyristors are shunted by the combination of a current limiting resistor in series with another switching means which is turned on before enabling said control means.
Claim 17
Dependent Claim
30 words
The switching means of claim 8 in which the duration of said first firing signal is at least as long as any conducting interval of said first set of thyristors.
References Cited (Backward Citations)
US3098949A
Cited
US3350568A
Cited
US3308370A
Cited
US3328606A
Cited
US3369154A
Cited
US3454834A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-25 | 1974-07-27 | 1975-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-25 | 1978-07-27 | 1979-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-25 | 1982-07-27 | 1983-01-26 | $7700.00 | Window Closed / Lapsed |