Parallel counter

Claim 2

In combination: a plurality n of bistable circuits having set and reset states and arranged in a predetermined ordered sequence; a plurality of coincidence gates each having a first input connection for receiving pulses to be counted; means coupling an output of each bistable circuit to a second input of different ones of said gates to enable such gates in response to the reset state of such bistable circuit; means responsive to a pulse at said first input to an enabled gate actuating such gate for simultaneously setting the bistable circuit coupled thereto and resetting all of said bistable circuits of lower order of significance in said sequence; and means responsive to said resetting of a bistable circuit inhibiting all of said gates of higher order of significance in said sequence.

Claim 3

In combination: a plurality of bistable circuits arranged in a predetermined ordered sequence and each having set and reset states of operation, each of said bistable circuits comprising a stage of a counting arrangement; means responsive to input pulses indicating the one of the bistable circuits in the lowest ordered position of said sequence in a reset state; and means coupled to said indicating means and responsive thereto for setting said one bistable circuit and resetting all other of said bistable circuits in lower ordered positions of said sequence whereby the states of said bistable circuits after each input pulse comprise a binary coded representation of the number of input pulses received subsequent to an all-reset state for said bistable circuits.

Claim 4

In combination: a plurality of bistable circuits arranged in a predetermined ordered sequence and each having set and reset states of operation, each of said bistable circuits comprising a stage of a counting arrangement; means responsive to input pulses indicating the one of the bistable circuits in the lowest ordered position of said sequence in a reset state; and means coupled to said indicating means and responsive thereto for setting said one bistable circuit and resetting all other of said bistable circuits in lower ordered positions of said sequence whereby the states of said bistable circuits after each input pulse comprise a binary coded representation of the number of input pulses received subsequent to an all-reset state for said bistable circuits.

Claim 5

The combination in accordance with claim 2 in which: said indicating means comprises n sections of gating means with each section corresponding to a different stage of said counting arrangement, each of said sections comprising a coincidence gate having active and disabled states, said gate having a first input connection for receiving said input pulses and haviNg a second input connection for enabling said coincidence gate in response to the reset state for the corresponding bistable circuit of such section; and said setting and resetting means comprises at each of said coincidence gates an output connection for setting the corresponding bistable circuit of such stage and resetting all bistable circuits in stages in lower orders of significance.

Claim 6

The combination in accordance with claim 3 in which said indicating means further comprises, means responsive to the resetting of one of said bistable circuits inhibiting all gating means sections in positions of higher orders of significance in said sequence.

Claim 7

The combination in accordance with claim 3 in which: additional gating means are provided with input connections coupled from all of said n gating means sections; and means couple an output of said additional gating means to reset all said bistable circuits in response to an input pulse following the attainment of an all-set state of said bistable circuits.

Claim 8

The combination in accordance with claim 2 in which, said counting arrangement is free of lumped reactive elements.

Claim 9

The combination in accordance with claim 2 in which, said counting arrangement is built up of transistor-diode NAND logic gates each having substantially the same predetermined operating time delay.

Claim 10

The combination in accordance with claim 2 in which: each of said bistable circuits has setting input connections and resetting input connections to which input signals must be applied for setting or resetting, respectively, such bistable circuit; said bistable circuits and said indicating means are built up from transistor-diode logic circuits only; and said setting means comprises direct wire connections between an output of said indicating means and said setting input of said one of said bistable circuits and said resetting inputs of said lower order bistable circuits.

Claim 11

The combination in accordance with claim 2 in which, said counting arrangement operates in a single phase mode whereby each input pulse thereto advances the count by one.

Claim 12

The combination in accordance with claim 3 in which said indicating means further comprises: an additional section of gating means including a further coincidence gate having active and disabled states, said further coincidence gate having a first input connection for receiving said input pulses and having a second input connection for enabling such gate in response to the simultaneous set state in all of said bistable circuits; and means coupling the output of said further coincidence gate to reset all of said bistable circuits.

Claim 13

The combination in accordance with claim 3 in which each of said n sections of gating means further comprises: first, second, and third logic gates each having disabled and active states; said first gate connected to be responsively activated by the coincidence of a disabled state of all said coincidence gates of other ones of said sections and of an enabling signal from a section of lower order of significance in said sequence; said second gate connected to be responsively activated by the coincidence of the disabled state of said first gate of the same section of said gating means and of the disabled state of the coincidence gate of said same section, said second gate having an output connection to said second input of the last-mentioned coincidence gate; and said third gate connected to be responsive to a disabled state of said second gate for supplying said enabling signal to said first gate of each of said sections in positions of higher order of significance in said sequence.

Claim 14

The combination in accordance with claim 3 in which each of said n sections of gating means further comprises: first and second logic gates each having disabled and active states; said first gate being connected to be responsively activated by the coincidence of the disabled state of all oF said coincidence gates of said sections of higher orders in said sequence and of a reset state in the bistable circuit of the same stage in said counting arrangement for disabling said coincidence gate in sections of higher order of significance in said sequence; and said second gate being connected to be responsively activated by the coincidence of the disabled state of the coincidence gate of the same stage of said counting arrangement and the set state of the bistable circuit of the same stage of said counting arrangement for disabling the last-mentioned coincidence gate.

Claim 15

In combination: a plurality n of bistable circuits having set and reset states and arranged in a predetermined ordered sequence; means indicating the one of said bistable circuits in the lowest ordered position of said sequence which is also in said reset state, said indicating means having n output circuits each corresponding to a different one of said bistable circuits, said indicating means producing a pulse on only the one of said output circuits corresponding to said one bistable circuit; and means coupling said pulse to set said one bistable circuit and to reset all bistable circuits of lower order of significance in said sequence.

Claim 16

In combination: a plurality n of bistable circuits having set and reset states and arranged in a predetermined ordered sequence; means indicating the one of said bistable circuits in the lowest ordered position of said sequence which is also in said reset state, said indicating means having n output circuits each corresponding to a different one of said bistable circuits, said indicating means producing a pulse on only the one of said output circuits corresponding to said one bistable circuit; and means coupling said pulse to set said one bistable circuit and to reset all bistable circuits of lower order of significance in said sequence.