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US3555185A Expired / Lapsed US ⏱️ 0.0 years remaining

Synchronizing pulse comparator circuitry

Assignee: Central Dynamics Ltd
•
Filing: 1968-01-05
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Granted: 1971-01-12
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Expires: 1988-01-05
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Abstract

Abstract A circuit for comparing two trains of synchronizing pulses is disclosed wherein the circuitry determines whether the time displacement between the trains is within a predetermined limit, the limit being adjustable. The above circuit comprises a comparator to which is applied the two pulse trains. The output of the comparator is a pulse whose width is a direct function of the displacement. This pulse is applied to an invertor and a monostable multivibrator, the pulse width of which is adjustable. The monostable multivibrator output and the invertor output are applied to a bistable multivibrator. The positive-going, leading edge of the monostable multivibrator output sets the bistable multivibrator and the positive-going, trailing edge of the invertor output pulse resets the bistable multivibrator. The output pulses of the monostable and bistable multivibrator are applied to a second comparator which generates an output alarm signal whenever the bistable multivibrator output signal is greater in time duration than the monostable multivibrator output signal. The occurence of an alarm signal at the output of the second comparator indicates that the time displacement between the pulse trains is greater than the predetermined limit established by the adjustable pulse width of the monostable multivibrator output signal. The second comparator output signal is applied to a second monostable multivibrator which detects the occurrence of an output signal from the second comparator even though the width pulse thereof is very slight. The second monostable multivibrator output signal is then applied to an integrator which provides an output signal only after a predetermined number of pulses of the two trains are out of synchronization. The integrator output signal is then applied to an appropriate control device.

Inventors

  • 👤 Ole Skrydstrup
  • 👤 Bjorn Larsen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 17:10
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073; H03; H03K; H03K5/00; H03K5/22; H03K5/26

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 190 words
Pulse comparator circuitry for detecting a nonsynchronous condition between at least two pulses of equal width, said circuitry comprising: first comparator means responsive to said two pulses for generating a first comparator means output pulse the width of which approximately equals the time displacement between said two pulses; monostable means responsive to the comparator output pulse for generating a monostable means output pulse, the pulse width of which establishes the greatest detectable time difference between said two pulses; bistable means responsive to the output pulses from said monostable means and said first comparator means for producing a bistable means output pulse, the leading edge of which is in substantial time coincidence with the leading edge of the monostable means output signal and the width of which approximately equals said time difference between the leading edges of said two pulses of equal width and; second comparator means responsive to the output pulses from said first monostable means and said bistable means for generating an alarm signal indicative of said nonsynchronous condition whenever the width of the bistable means output pulse is greater than the width of the monostable means output pulse.
Claim 2
Dependent Claim 190 words
Pulse comparator circuitry for detecting a nonsynchronous condition between at least two pulses of equal width, said circuitry comprising: first comparator means responsive to said two pulses for generating a first comparator means output pulse the width of which approximately equals the time displacement between said two pulses; monostable means responsive to the comparator output pulse for generating a monostable means output pulse, the pulse width of which establishes the greatest detectable time difference between said two pulses; bistable means responsive to the output pulses from said monostable means and said first comparator means for producing a bistable means output pulse, the leading edge of which is in substantial time coincidence with the leading edge of the monostable means output signal and the width of which approximately equals said time difference between the leading edges of said two pulses of equal width and; second comparator means responsive to the output pulses from said first monostable means and said bistable means for generating an alarm signal indicative of said nonsynchronous condition whenever the width of the bistable means output pulse is greater than the width of the monostable means output pulse.
Claim 3
Dependent Claim 19 words
Circuitry as in claim 1 where said monostable means includes means for adjusting the width of its output signal.
Claim 4
Dependent Claim 28 words
Circuitry as in claim 2 including invertor means responsive to said first comparator means output pulse for developing one of the two signals applied to said bistable means.
Claim 5
Dependent Claim 35 words
Circuitry as in claim 3 where said bistable means is set by the leading edge of said monostable means output signal and it is reset by the trailing edge of said invertor means output signal.
Claim 6
Dependent Claim 44 words
Circuitry as in claim 1 including second monostable means for detecting the presence of said alarm signal from said second comparator means no matter how slight the width of said alarm signal and for generating a signal of sufficient width to insure detection thereof.
Claim 7
Dependent Claim 44 words
Circuitry as in claim 1 where one of said two pulses is one of a train of television synchronizing pulses generated by a standard clock source and where the other is one of a train of television synchronizing pulses separated from a video signal.
Claim 8
Dependent Claim 26 words
Circuitry as in claim 6 including integrator means for detecting the presence of a predetermined number of said alarm signals over a predetermined period of time.
Claim 9
Dependent Claim 47 words
Circuitry as in claim 1 where one of said two pulses is one of a first train of television synchronizing pulses separated from a first video signal and where the other is one of a second train of television synchronizing pulses separated from a second video signal.

References Cited (Backward Citations)

US2858425A Cited
US3058063A Cited
US3265974A Cited
US3430148A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-01-11 1974-07-13 1975-01-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-01-11 1978-07-13 1979-01-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-01-11 1982-07-13 1983-01-12 $7700.00 Window Closed / Lapsed

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