Patent US3292847A successfully refreshed from Google Patents.
US3553497A
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US
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Bistable flip-flop circuit with improved control of clock threshold
Assignee: Stewart Warner Corp
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Filing: 1968-03-01
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Granted: 1971-01-05
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Expires: 1988-03-01
Abstract
Abstract A bistable flip-flop circuit for use preferably in monolithic semiconductor integrated circuits having a master flip-flop at the circuit input and a slave output at the circuit output with coupling transistors between the two master and slave flip-flops. The emitters of the transistors coupled through a resistor to the clock pulse input so that the master flip-flop changes state responsive to the rise time of the clock pulse and the slave flip-flop changes state during the fall time of the clock pulse throughout an extended temperature range.
Inventors
- 👤 William C Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 03:36
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/289
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
236 words
A bistable memory circuit having an output changeable from one stable state to its opposite stable state responsive to pulses received at its input from a pulse source comprising a master flip-flop coupled to said input and having a pair of oppositely oriented signal outputs, said master flip-flop operable responsive to the leading edge of said pulses to change its state, a slave flip-flop coupled to said circuit output and having a pair of oppositely oriented signal inputs, a first coupling transistor having its base coupled to one of said master outputs and its collector coupled to one of said slave inputs and operable responsive to said master flip-flop assuming one of its states to conduct to cause said slave flip-flop to assume one state, a second coupling transistor having its base coupled to the other of said master flip-flop outputs and its collector connected to the other of said slave inputs and operable responsive to said master flip-flop assuming its opposite state to conduct to cause said slave flip-flop to assume its opposite state, means responsive to the change of state of said slave flip-flop for rendering said coupling transistors nonconductive, and a fixed resistance connecting the emitters of said coupling transistors to said pulse source, said resistance having a value to insure that said coupling transistors begin conducting responsive only to the lagging edge of said pulses over the range of expected ambient Temperatures.
Claim 2
Dependent Claim
236 words
A bistable memory circuit having an output changeable from one stable state to its opposite stable state responsive to pulses received at its input from a pulse source comprising a master flip-flop coupled to said input and having a pair of oppositely oriented signal outputs, said master flip-flop operable responsive to the leading edge of said pulses to change its state, a slave flip-flop coupled to said circuit output and having a pair of oppositely oriented signal inputs, a first coupling transistor having its base coupled to one of said master outputs and its collector coupled to one of said slave inputs and operable responsive to said master flip-flop assuming one of its states to conduct to cause said slave flip-flop to assume one state, a second coupling transistor having its base coupled to the other of said master flip-flop outputs and its collector connected to the other of said slave inputs and operable responsive to said master flip-flop assuming its opposite state to conduct to cause said slave flip-flop to assume its opposite state, means responsive to the change of state of said slave flip-flop for rendering said coupling transistors nonconductive, and a fixed resistance connecting the emitters of said coupling transistors to said pulse source, said resistance having a value to insure that said coupling transistors begin conducting responsive only to the lagging edge of said pulses over the range of expected ambient Temperatures.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-04 | 1974-07-06 | 1975-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-04 | 1978-07-06 | 1979-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-04 | 1982-07-06 | 1983-01-05 | $7700.00 | Window Closed / Lapsed |