Abstract A semiconductor circuit for sampling and holding a voltage level appearing across a device which cannot be loaded without disturbing the voltage to be sampled, the illustrative circuit employing two field-effect transistors (F.E.T.), and taking advantage of their virtually-infinite input impedance characteristics to avoid loading. The first F.E.T. is connected to serve as the sampling voltage-level input, and the second F.E.T. is connected to sample the output of the circuit and to compensate for nonlinearity and temperature-sensitivity characteristics by driving, together with the first F.E.T., a differential amplifier having a high gain and a high degree of inverse feedback, the output of the differential amplifier following precisely the voltage level being sampled, but having a lower impedance characteristic which enables it to drive utilization circuits which may draw considerable currents. The charge on the storage capacitor which serves as the input device is updated by another F.E.T. serving as a switch.
A circuit for sampling without loading an input voltage and for delivering an output voltage precisely matching the level of said input voltage, comprising: a. plus and minus power supply means; b. first and second field-effect transistors, each having a gate, and a source and drain path, the gate of the first transistor being connected to receive said input voltage; c. differential amplifier means having two input terminals and an output delivering said output voltage; d. coupling means comprising similar separate voltage divider means having end terminals connected across said power supply means and each having upper and lower intermediate terminals, the upper terminals being respectively connected to be driven by the source and drain paths of said transistors and the lower intermediate terminals being respectively connected to drive the respective input terminals of the differential amplifier means; e. means directly coupling the output of the differential amplifier means to the gate of the second transistor; and f. potEntiometer means connected across said power supply means having a tap, and a resistor connected between said tap and the lower intermediate terminal of one of said voltage divider means, the tap on the potentiometer being adjustable to make the output voltage of the differential amplifier means equal to zero when said input voltage equals zero.
Claim 2
Dependent Claim
214 words
A circuit for sampling without loading an input voltage and for delivering an output voltage precisely matching the level of said input voltage, comprising: a. plus and minus power supply means; b. first and second field-effect transistors, each having a gate, and a source and drain path, the gate of the first transistor being connected to receive said input voltage; c. differential amplifier means having two input terminals and an output delivering said output voltage; d. coupling means comprising similar separate voltage divider means having end terminals connected across said power supply means and each having upper and lower intermediate terminals, the upper terminals being respectively connected to be driven by the source and drain paths of said transistors and the lower intermediate terminals being respectively connected to drive the respective input terminals of the differential amplifier means; e. means directly coupling the output of the differential amplifier means to the gate of the second transistor; and f. potEntiometer means connected across said power supply means having a tap, and a resistor connected between said tap and the lower intermediate terminal of one of said voltage divider means, the tap on the potentiometer being adjustable to make the output voltage of the differential amplifier means equal to zero when said input voltage equals zero.